1. Introduction：

IP is a Binary-PSK demodulator based on a multiply-filter-divide architecture.   The design is robust and flexible and allows easy connectivity to an external  ADC.

As the the carrier recovery circuit is open-loop, there is no feedback path or loop-filter to configure.  This results in an extremely simple circuit with a very fast carrier acquisition time.  The only requirement is that the user set the desired symbol period and a suitable threshold level for the bit decisions at the symbol decoder.  The other design parameters including carrier   frequency,   symbol   rate   and   sampling   frequency   should   be specified by the user before delivery of the IP Core 1 .

The input data samples are 16-bit signed (2's complement) values that are synchronous with the system clock.  Input values are sampled on the rising edge of clk when en is high.

 

Application

• Robust, low bandwidth RF applications for small FPGA devices
• SRD and ISM band devices
• Medium to long-range telemetry
• Software radio

2. License Price：

By Quotes

Multiple License : NO

3. Clock Rate：

200 MHz

4. Logic Gate Count：

None

5. Technology：

None

6. Version：

1.0