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| Wide band 3Ghz-6GHz integer phase-locked loop | By Quotes | 1.080 M μm^2 | 6 GHz | 65 nm |  |
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| It is an integer-N phase-locked loop frequency synthesizer (PLL) based on fully integrated wide band LC-VCO with range from 3 GHz to 6 GHz with good phase noise performance. IP technology: TSMC CMOS CRN65LP. | Introduction | |||||
| Wide band 3Ghz-6GHz fractional phase-locked loop | By Quotes | 1.100 M μm^2 | 6 GHz | 65 nm | |
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| It is a phase-locked loop frequency synthesizer (PLL) with integer-N/fractional-N modes based on fully integrated wide band LC-VCO with range from 3 GHz to 6 GHz with good phase noise performance. IP technology: TSMC CMOS CRN65LP. | Introduction | |||||
| 20 to 300 MHz integer-N frequency synthesizer | By Quotes | 85.000 K μm^2 | 300 MHz | None | |
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| It is an integer-N PLL frequency synthesizer that generates a 20MHz to 300MHz output clock. The IP block uses 8MHz to 16MHz reference clock at CKREF. Build-in reference frequency detector indicates when reference frequency is too low. IP technology: SilTerra CMOS18G. | Introduction | |||||
| Power Controller | By Quotes | 0.165 μm^2 | None | 90 nm | |
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| It is a configurable core that is configured for each specific SoC, delivering all the necessary auxiliary supply, monitoring and protection. | Introduction | |||||
| Bluetooth 5.2 | By Quotes | None | None | 22 nm | |
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| It's ultra-low-power RF transceiver IP and is designed to meet 2.4 GHz standards. | Introduction | |||||
| Bluetooth 5.2 Dual | By Quotes | None | None | 22 nm | |
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| This bluebooth is of the lowest power consumption. | Introduction | |||||
| MIPI PHY | By Quotes | None | None | None | |
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| This product offers complete debug facilities to validate Application processors with MIPI interfaces, MIPI Cameras and MIPI displays. | Introduction | |||||
| RC Oscillator | By Quotes | 0.970 μm^2 | 10.2 Hz | 3 nm | |
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| The digitally controlled RC oscillators optimized for ultra low power applications. Application: • Hand held devices • Wireless Power devices • Battery powered stand-by devices | Introduction | |||||
| PLL 3000M UMC 28 nm logic and Mixed-Mode HPC process | By Quotes | 92.400 K μm^2 | 27 MHz | 28 nm | |
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| It generates a stable high-speed clock from an external slower reference clock signal. It integrates a Voltage-Controlled Oscillator (VCO), a Phase-Frequency Detector (PFD), a Low-Pass Filter (LPF), a 9-bit programmable loop divider, a 2-bit programmable pre-divider and associated support circuitry. This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process, and it supports an operating voltage ranging from 0.81 V to 0.99 V with an operating junction temperature ranging between -40 °C and 125 °C. It accepts FREF frequency ranging from 6 MHz to 27 MHz and generates the output frequency up to 3000 MHz. | Introduction | |||||
| PLL 2000M UMC 28 nm logic and Mixed-Mode HPC process | By Quotes | 230.000 μm^2 | 2 GHz | 28 nm | |
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| A Phase-Locked Loop (PLL) circuit used to generate the high-speed clock with an operating frequency up to 2000 MHz. This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process. It can be integrated into a chip to generate an accurate clock. | Introduction | |||||
| μIP | Price | Logic Gate Count | Clock Rate | Technology | Ratings | |
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