This is an USB 3.1 Gen1 dual-role controller, which is compliant to USB 2.0/USB 3.1 Gen1 specifications. The controller can act as a standard
host or peripheral for easy system implementation. The role can be selected via static pin selection.
This is a universal serial bus (USB) 2.0 On-The-Go (OTG) Controller, which can play dual-role, as a host or a device controller. When it acts as a host, it contains a USB host controller to support all speed transactions.
Designed to work with a wide variety of SPI bus variants, the core supports run-time control of several SPI protocol parameters. For example, the SPI frame width can be 1 to 4 bytes, the
most significant bit position in a frame, serial clock phase and polarity are all software- programmable. In master mode the core can control up to 32 slaves. A software controllable clock generator derives the serial clock for master mode, by dividing the frequency of a clock line dedicated for that purpose
The CAN protocol uses a multi-master bus configuration for the transfer of frames be- tween nodes of the network and manages error handling with no burden on the host processor. The core enables the user to set up economic and reliable links between vari- ous components. It appears as a memory-mapped I/O device to the host processor, which accesses the CAN core to control the transmission or reception of frames.
The CAN core is easy to use and integrate, featuring programmable interrupts, data and baud rates; a configurable number of independently programmable acceptance filters; and a generic processor interface or optionally an AMBA APB, or AHB-Lite interface. It imple- ments a flexible buffering scheme, allowing fine-tuning of the core size to satisfy the requirements of each specific application
PLL 3000M UMC 28 nm logic and Mixed-Mode HPC process
92.400 K μm^2
It generates a stable high-speed clock from an external slower reference clock signal. It integrates a Voltage-Controlled Oscillator (VCO), a Phase-Frequency Detector (PFD), a Low-Pass Filter (LPF), a 9-bit programmable loop divider, a 2-bit programmable pre-divider and associated support circuitry. This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process, and it supports an operating voltage ranging from 0.81 V to 0.99 V with an operating junction temperature ranging between -40 °C and 125 °C. It accepts FREF frequency ranging from 6 MHz to 27 MHz and generates the output frequency up to 3000 MHz.
PLL 2000M UMC 28 nm logic and Mixed-Mode HPC process
A Phase-Locked Loop (PLL) circuit used to generate the high-speed clock with an operating frequency up to 2000 MHz.
This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process.
It can be integrated into a chip to generate an accurate clock.
PLL 1600M UMC 28 nm logic and Mixed-Mode HPC process
A Phase-Locked Loop (PLL) with an operating frequency ranging from 200 MHz to 1600 MHz.
This PLL is designed with the UMC 28 nm logic and Mixed-Mode HPC process.
It can be integrated into a chip to generate a high-speed clock.
The embedded divide-by-4 loop divider allows users to boost the output frequency of up to 1600 MHz.
PLL 800M UMC 28 nm logic and Mixed-Mode HPC process
It is a 28-nm low-power spread spectrum clock generator that supports an operating frequency ranging from 400 MHz to 800 MHz and from 200 MHz to 400 MHz.
This SSCG is programmable to perform the frequency synthesis and spread-spectrum function for the Electro Magnetic Interference (EMI) reduction in various ASIC designs.
PLL 1300M UMC 28 nm logic and Mixed-Mode HPC process
109.850 K μm^2
It is used to generate a stable, high-speed clock from an external slower clock signal. It integrates one Voltage-Controlled Oscillator (VCO), one Phase-Frequency Detector (PFD), one Low-Pass Filter (LPF), one 8-bit programmable divider, and other associated support circuitries. This PLL supports an operating voltage ranging from 0.81 V to 0.99 V with an operating junction temperature ranging between -40 °C and 125 °C. This IP uses the input operating frequency of PFD ranging from 6 MHz to 25 MHz and generates the output frequency ranging from 25 MHz to 1300 MHz.
The jitter performance of a PLL is highly dependent on the floor plan of ASIC. Because PLL is a sensitive cell when integrated into an ASIC design, the best way to maximize its capacity is to keep PLL away from the noisy blocks in the core region, such as the memory block and the high-driving logic circuit, and the I/O region, such as the high-driving I/O. This PLL must be placed around the I/O area. Providing sufficient space between this PLL and the noisy blocks is a simple and effective approach to reduce the coupled substrate noise.