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Power Controller By Quotes 0.165 μm^2 None 90 nm  
It is a configurable core that is configured for each specific SoC, delivering all the necessary auxiliary supply, monitoring and protection.  Introduction
Bluetooth 5.2 By Quotes None None 22 nm  
It's ultra-low-power RF transceiver IP and is designed to meet 2.4 GHz standards.  Introduction
Bluetooth 5.2 Dual By Quotes None None 22 nm  
This bluebooth is of the lowest power consumption.  Introduction
MIPI PHY By Quotes None None None  
This product offers complete debug facilities to validate Application processors with MIPI interfaces, MIPI Cameras and MIPI displays.  Introduction
RC Oscillator By Quotes 0.970 μm^2 10.2 Hz 3 nm  
The digitally controlled RC oscillators optimized for ultra low power applications.                                Application:                                            • Hand held devices • Wireless Power devices • Battery powered stand-by devices Introduction
USB 3.1 GEN1 DUAL-ROLE CONTROLLER By Quotes None 30 MHz None  
This is an USB 3.1 Gen1 dual-role controller, which is compliant to USB 2.0/USB 3.1 Gen1 specifications. The controller can act as a standard host or peripheral for easy system implementation. The role can be selected via static pin selection. Introduction
USB 2.0 ON-THE-GO CONTROLLER By Quotes 75.000 K Gates 200 MHz None  
This is a universal serial bus (USB) 2.0 On-The-Go (OTG) Controller, which can play dual-role, as a host or a device controller. When it acts as a host, it contains a USB host controller to support all speed transactions. Introduction
Octal SPI Master/Slave Controller By Quotes 4.641 K Gates 500 MHz None  
Designed to work with a wide variety of SPI bus variants, the core supports run-time control of several SPI protocol parameters. For example, the SPI frame width can be 1 to 4 bytes, the most significant bit position in a frame, serial clock phase and polarity are all software- programmable. In master mode the core can control up to 32 slaves. A software controllable clock generator derives the serial clock for master mode, by dividing the frequency of a clock line dedicated for that purpose   Introduction
CAN 2.0 & CAN FD Bus Controller Core By Quotes 12.000 K Gates None None  
The CAN protocol uses a multi-master bus configuration for the transfer of frames be- tween nodes of the network and manages error handling with no burden on the host processor. The core enables the user to set up economic and reliable links between vari- ous components. It appears as a memory-mapped I/O device to the host processor, which accesses the CAN core to control the transmission or reception of frames. The CAN core is easy to use and integrate, featuring programmable interrupts, data and baud rates; a configurable number of independently programmable acceptance filters; and a generic processor interface or optionally an AMBA APB, or AHB-Lite interface. It imple- ments a flexible buffering scheme, allowing fine-tuning of the core size to satisfy the requirements of each specific application   Introduction
BOSCH CAN 2.0A/B AND CAN FD 1.0 CONTROLLER By Quotes None None None  
The CAN controller is an I2C/APB compliant controller to act as a transmitter or receiver in the CAN bus.    Introduction
μIP Price Logic Gate Count Clock Rate Technology   Ratings

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