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| High Stable Timers IP | By Quotes | None | 0.8 MHz | None |  |
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| Timers are used for scheduling the different activities within the system. Timers generates interrupt in system and Operating system(OS) Schedules different Timers and maps them to different Interrupt Service Routine (ISR) to start on different interrupts. It can happen before starting a activity or application, OS configures a timers and give control to application to operate. On Interrupt trigger a interrupt, ISR kicks in and passes control back to OS. A Miss Function on this block can make system to mis-behave a lot. These section explains issues with normal timers and benefits of this high stable timers over conventional timers. -The Problem with Current Technology Timers carry large counters, Registers, clocks pre-scalers and synchronizations and all these are built by Simple Components which do not have any stability. If the SOC is exposed to different hazards like radiations, sparks or other events. These logics can be corrupted within counters and registers carrying configuration. This may result in corruption in stored configurations or counters or data or control passing by and can make interrupts to be generated fast or slower rate or even stopped. If system gets faster interrupt, then expected will make control to passed back to Operating system(OS) from the application or much before the application actually able to complete the task. This make system to not able to perform the required task. if interrupts generation is slowed down, will keep the OS waiting much longer to get control and application work is finished long back. This can make system to slow down or Hang. -The Solution High Stable Timers from GreenIPCore can sustain across all system un-stability and misbehavior problems. This Timers is strengthening system against any kind of dirty Electromagnetic noise and capable of protecting the System operation without disruption. The Timers is constructed with high stable components. The High Stable Timers shown above will not fail due to any hazardous event. | Introduction | |||||
| 0.13um Real Time Clock | By Quotes | None | 32 KHz | 130 nm | |
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| The RTC is a 0.13μm Real-Time-Clock cell that provides multiple clocks. This RTC provides an operating voltage range of 2.7V ~ 3.3V, and an operating junction temperature range of -40˚ ~ 125℃. | Introduction | |||||
| I2C Slave Serial Interface Controller | By Quotes | None | 300 MHz | None | |
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| Slave serial controller compatible with the popular Philips® I2C standard. Permits an I2C Master to communicate with your ASIC device via a set of user-defined config and status registers. Supports standard (100 kbits/s), fast (400 kbits/s) and custom rates in excess of 4 Mbits/s. Applications I2C slave communication via your ASIC Inter-chip board-level communications | Introduction | |||||
| I2C Master Serial Interface Controller | By Quotes | None | 300 MHz | None | |
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| Master serial controller compatible with the popular Philips® I2C standard. Features a simple command interface and permits multiple I2C slaves to be controlled directly from ASIC device. Supports standard (100 kbits/s), fast (400 kbits/s) and custom data rates well above 4 Mbits/s. Setup and hold-times on the SDA pin are fully configurable. Applications Inter-chip board-level communications Standard 2-wire comms between a wide range of peripherals, MCUs and COTs ICs | Introduction | |||||
| UART Serial Interface Controller | By Quotes | None | 300 MHz | None | |
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| UART compatible Serial Interface Controller with receive and transmit FIFOs and support for all standard bit rates from 9600 to 921600 baud. Applications UART Communications RS232, RS422, RS485 etc. Micro-controller interfacing | Introduction | |||||
| One Wire Communication | 1200 Points | 1.500 K Gates | 100 MHz | 130 nm | |
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| In some particular application, few pin count but still need chip to chip communication. This IP use one wire bi-direction (open drain) to communication. Just like UART , it is consist of one TX and one RX. User can define their own payload freedomly. All devices are connecting through open-drain pull high bus. Every device can send data to others actively. Waveform Application - Analog IC debug - MCU program port - Low pin count IC | Introduction | |||||
| Asynchronous I2C Slave | 999 Points | 578.000 Gates | 100 MHz | 130 nm | |
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| Unlike Synchronous type I2C slave design need clock to work. This Asynchronous type don’t need base clock . It is very power saving in some application Application : - Power manager IC - Sensor IC - Software wakeup requirement system | Introduction | |||||
| SPI slave in mode 2 | 1000 Points | 254.000 Gates | 192 MHz | 130 nm | |
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| The Serial Peripheral Interface (SPI) bus, established by Motorola, is a synchronous serial data link. It operates in master/slave and full duplex styles. That is, when a master device initiates a transaction and communicates with a certain slave device, they exchange data bit-by-bit. Furthermore, the single master communication is applied to the SPI bus. Thus, there is always a single master device (with one or more slave devices) on it. The SPI bus contains 4 wires, with each named SCK, MOSI, MISO and SS_n respectively. You may also find alternative naming conventions elsewhere. The following table lists their functions and directions: The typical SPI bus architecture is designed as follows: When the SPI master device wants to communicate with a certain slave device, it asserts the SS_n line of that slave device, and then exchange data using the MOSI and MISO lines based on the toggling SCK line. With clock polarity (CPOL) and clock phase (CPHA) set to different values, the SPI bus can operate in 4 modes. These modes are listed in the following table, where provide means that the communicating master and slave devices provide data on the MOSI and MISO lines respectively on the other hand, capture means that the communicating master and slave devices capture data on the MISO and MOSI lines respectively: | Introduction | |||||
| SPI slave in mode 1 | 1000 Points | 276.000 Gates | 285 MHz | 130 nm | |
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| The Serial Peripheral Interface (SPI) bus, established by Motorola, is a synchronous serial data link. It operates in master/slave and full duplex styles. That is, when a master device initiates a transaction and communicates with a certain slave device, they exchange data bit-by-bit. Furthermore, the single master communication is applied to the SPI bus. Thus, there is always a single master device (with one or more slave devices) on it. The SPI bus contains 4 wires, with each named SCK, MOSI, MISO and SS_n respectively. You may also find alternative naming conventions elsewhere. The following table lists their functions and directions: The typical SPI bus architecture is designed as follows: When the SPI master device wants to communicate with a certain slave device, it asserts the SS_n line of that slave device, and then exchange data using the MOSI and MISO lines based on the toggling SCK line. With clock polarity (CPOL) and clock phase (CPHA) set to different values, the SPI bus can operate in 4 modes. These modes are listed in the following table, where provide means that the communicating master and slave devices provide data on the MOSI and MISO lines respectively on the other hand, capture means that the communicating master and slave devices capture data on the MISO and MOSI lines respectively: | Introduction | |||||
| SPI slave in mode 0 | 1000 Points | 274.000 Gates | 243 MHz | 130 nm | |
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| The Serial Peripheral Interface (SPI) bus, established by Motorola, is a synchronous serial data link. It operates in master/slave and full duplex styles. That is, when a master device initiates a transaction and communicates with a certain slave device, they exchange data bit-by-bit. Furthermore, the single master communication is applied to the SPI bus. Thus, there is always a single master device (with one or more slave devices) on it. The SPI bus contains 4 wires, with each named SCK, MOSI, MISO and SS_n respectively. You may also find alternative naming conventions elsewhere. The following table lists their functions and directions: The typical SPI bus architecture is designed as follows: When the SPI master device wants to communicate with a certain slave device, it asserts the SS_n line of that slave device, and then exchange data using the MOSI and MISO lines based on the toggling SCK line. With clock polarity (CPOL) and clock phase (CPHA) set to different values, the SPI bus can operate in 4 modes. These modes are listed in the following table, where provide means that the communicating master and slave devices provide data on the MOSI and MISO lines respectively on the other hand, capture means that the communicating master and slave devices capture data on the MISO and MOSI lines respectively: | Introduction | |||||
| μIP | Price | Logic Gate Count | Clock Rate | Technology | Ratings | |
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