1. Introduction：

This is a polyphase decimation filter that permits the down-sampling of an input signal by any power of 2. The filter core is organized as a highly optimized systolic array, allowing the user to specify very large decimation factors while keeping resource costs to a minimum.

 

Input data is sampled on the rising clock-edge of clk when CLK_EN  is active high. Internally, the samples are filtered and decimated then presented at the output interface, Y_OUT.The output signal EN_OUT is the output clock-enable signal that indicates when an output sample is valid.

 

Application

• Decimation by a wide range of factors from 2 to 2^N
• Reduction of input sample rate to make subsequent signal processing easier
• Decimation of signals after digital-down-conversion

 

 

2. License Price：

By Quotes

Multiple License : NO

3. Clock Rate：

300 MHz

4. Logic Gate Count：

None

5. Technology：

None

6. Version：

1.0