1. Introduction：

The IP Core is a studio quality 24-bit RGB video deinterlacer capable of generating progressive output video at any resolution up to 2¹⁶ x 2¹⁶  pixels. The design is fully programmable and supports any desired interlaced video format.

The design allows for three possible deinterlacing schemes. These are: weave, bilinear interpolation or motion-adaptive interpolation. The weave approach applies no filtering and may be useful to obtain a 'raw' interlaced format for subsequent processing. The other two methods are classed as 'inter-field' interpolation methods as spatial filtering is performed between both odd and even fields to achieve a clean and progressive output. The relative merits and disadvantages of each scheme are discussed further into the document.

The deinterlacer core features a fully integrated video frame buffer. This buffer is completely 'elastic' and will dynamically skip and/or repeat frames depending on the input and output frame rates. All frame buffer management is handled internally with the provision of a simple memory interface for storing odd and even fields off-chip. The memory interface is 128-bits wide and is completely  generic. All memory transfers are sequential bursts of N x 128-bit words and may be adapted for connection to a variety of memory types such as SDRAM, DDR2 or DDR3.

Application

• Digital TV set-top boxes. Industrial imaging. Automotive, home and personal media solutions
• Conversion of 'legacy' SDTV formats to HDTV video formats
• Generating progressive RGB video via inexpensive PAL/NTSC decoder chips
• Studio-quality video de-interlacing

2. License Price：

By Quotes

Multiple License : NO

3. Clock Rate：

200 MHz

4. Logic Gate Count：

None

5. Technology：

None

6. Version：

1.0