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  • uIP: Digital Down Converter with configurable Decimation Filter
  • uIP ID: 452318041
  • μIP Type: Digital μIP
  • HDL: Verilog
  • Warranty: YES
  • Simulation Tool: Cadence NC-Verilog
  • Tool Version:
  • Design Format: RTL
  • Merge In Foundry: NO
    Designer Information
  • Member ID:7730998000300188
  • Designer Rating:
  • Feedback received:0
 

1. Introduction:

DDC is a complex-valued digital down-converter with a configurable number of decimation stages.  The design is ideal for high sample-rate applications and permits a digital input signal to be mixed-
down and re-sampled at a lower data rate.  The DDC is suitable for the down-conversion   of   any   digitally   modulated   signal   to   baseband   –   an essential step before digital processing.

The DDC features a high-precision 16-bit DDS oscillator for the digital mixing stage.   This oscillator is fully programmable and offers excellent phase and frequency resolution.  The digital mixing stage  is a complex multiplier that allows  the mixing of both real and imaginary (I/Q) inputs.  If only real inputs are required, then the imaginary input (q_in) should be tied low.

The output decimation stage features a configurable decimate-by-2N  poly-phase   filter   for   both   I   and   Q   channels.     Each   filter   stage   is   highly optimized to use only 12 multipliers while still achieving 80 dB of stop-band attenuation.

 

Application

  • Compatible with any digital modulation scheme - e.g. QPSK, BPSK, QAM, WiMAX, WCDMA, COFDM etc.
  • Conversion of IF signals to baseband frequencies for subsequent processing
  • Digital I/Q Demodulators

 

 


2. License Price:

By Quotes

Multiple License : NO


3. Clock Rate:

250 MHz


4. Logic Gate Count:

None


5. Technology:

None


6. Version:

1.0