1. Introduction：

The IP is an N-channel multiplexed FIR filter designed for high sample rate  applications  where  hardware  resources  are  limited. The main filter core is organized as a scalable systolic array permitting the user to specify large order filters without compromising maximum attainable clock-speed.

 

Essentially the filter functions as if it were 'N' separate FIR filters.  Each input sample is multiplexed into the filter at a sample rate equal to F_s /N, 
where F_s is the sampling frequency of the main filter core.   Likewise, output samples are updated at a frequency of  F_s /N.

 

The first sample into the filter is aligned by asserting the signal X_VALID high. The signal  Y_VALID_val  is asserted with the first valid output sample. Data samples are advanced in the pipeline on the rising clock-edge of clk when en is active high.  When en is low then all data samples are stalled.  The clock-enable signal may be used to temporarily disable the filter - or possibly to modify the effective sampling frequency of the system clock.  If the clock-enable is not needed it is recommended that this signal be tied high as it will improve overall circuit performance.

 

Application

• Dual-channel inputs such as complex valued I/Q in digital communications systems
• High-speed filtering applications where hardware resources are limited
• General purpose FIR filters with odd or even numbers of taps

2. License Price：

By Quotes

Multiple License : NO

3. Clock Rate：

500 MHz

4. Logic Gate Count：

None

5. Technology：

None

6. Version：

1.0