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  • uIP: 10/100/1000 Ethernet Media Access Controller
  • uIP ID: 1642394970
  • μIP Type: Digital μIP
  • HDL: Verilog
  • Warranty: YES
  • Simulation Tool: Synopsys VCS
  • Tool Version:
  • Design Format: RTL
  • Merge In Foundry: NO
    Designer Information
  • Member ID:9901018000700099
  • Designer Rating:
  • Feedback received:0
 

1. Introduction:

The MAC-1G/MAC is a synthesizable HDL core of a high-speed LAN controller. It implements Carrier Sense  Multiple  Access  with  Collision  Detection  (CSMA/CD)  algorithms  defined  by  the  IEEE  802.3 standard for media access control over the 10Mbps, 100Mbps and 1Gbps Ethernet. Communication  with  an external  host  is implemented  via  a set  of Control  and Status  Registers  and the DMA controller for external shared RAM memory. For data transfers the MAC-1G/MAC operates as 
a DMA master. It automatically fetches from transmit data buffers and stores receive data buffers into external RAM with minimum CPU intervention. The linked list management enables the use of various memory allocation schemes. There is an interface for external dual port RAMs serving as configurable FIFO memories and there are separate memories for transmit and receive processes. Using the FIFOs additionally isolates the MAC-1G/MAC from an external host and provides resolution in case of latency of an external bus. 

 

Application

  • Network Interface Cards (NICs) 
  • Routers, switching hubs


2. License Price:

By Quotes

Multiple License : NO


3. Clock Rate:

125 MHz


4. Logic Gate Count:

None


5. Technology:

130 nm


6. Version:

1.0