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  • uIP: Clock divider by 3
  • uIP ID: 271798
  • μIP Type: Digital μIP
  • HDL: Verilog
  • Warranty: YES
  • Simulation Tool: Cadence NC-Verilog
  • Tool Version:
  • Design Format: Netlist
  • Merge In Foundry: NO
    Designer Information
  • Member ID:7520023000300058
  • Designer Rating:
  • Feedback received:0
 

1. Introduction:

There are 2 types of circuits in digital logic world. One is combinational, and the other is sequential. The difference between them is that the latter one has storage (memory) while the former one does not. Thus, in contrast to combinational circuits, whose output depends only on the current values of its inputs, the output of sequential circuits depends not only on the current values of its inputs but also on the past values of them. Based on the characteristic of sequential circuits, we can build counters. In addition, we can further build clock dividers with the counters we designed


2. License Price:

100 Points

Multiple License : YES

   - Discount for 2 ~ 5 license:5 %
   - Discount for 6 ~ 10 license:10 %
   - Discount for 11 ~ license:15 %


3. Clock Rate:

370 MHz


4. Logic Gate Count:

52 Gates


5. Technology:

130 nm


6. Version:

1.0