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  • uIP: One Wire Communication
  • uIP ID: 393005
  • μIP Type: Digital μIP
  • HDL: Verilog
  • Warranty: YES
  • Simulation Tool: Cadence NC-Verilog
  • Tool Version:
  • Design Format: Netlist
  • Merge In Foundry: NO
    Designer Information
  • Member ID:7020289000900558
  • Designer Rating:
  • Feedback received:0
 

1. Introduction:

In some particular application, few pin count but still need chip to chip communication. This IP use one wire bi-direction (open drain) to communication. Just like UART , it is consist of one TX and one RX. User can define their own payload freedomly.

 

All devices are connecting through open-drain pull high bus. Every device can send data to others actively.

Waveform

                       1_wave_form.jpg

 

 

 

 

Application
      - Analog IC debug
     - MCU program port
     - Low pin count IC


2. License Price:

1200 Points

Multiple License : YES

   - Discount for 2 ~ 5 license:5 %
   - Discount for 6 ~ 10 license:10 %
   - Discount for 11 ~ license:15 %


3. Clock Rate:

100 MHz


4. Logic Gate Count:

1.5 K Gates


5. Technology:

130 nm


6. Version:

1.0