Video Frame Buffer |
By Quotes |
None |
300 MHz |
None |
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VID_FB is a high-speed multi-format video frame buffer that asynchronously samples an input video stream and buffers it in an external memory. Output pixels are read out of the buffer and synchronised to the system clock domain.
The VID_FB will automatically adapt to different input and output frame rates. If the input frame rate is too high, then the VID_FB will cleanly drop or 'skip' an input frame. Likewise, if the output frame rate is higher than the input frame rate, then frames will be repeated 3 . The result is a system that seamlessly adapts to the different frame rates at the input and output of the VID_FB.
Applications
Buffering video frames in external memory
Real-time digital video applications
Genlocking of multiple video sources
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Introduction |
ITU-R BT.656 video encoder |
By Quotes |
None |
200 MHz |
None |
|
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ITU-R_BT is a digital video encoder with integrated colour-space converter. The encoder accepts 24-bit RGB pixels from sequential odd and even fields. These pixels are then mapped to the YCbCr colour-space and formatted correctly into a BT output stream.
The output of the encoder generates an industry standard ITU-R BT.656 format video stream together with a video_val signal that is asserted with the first valid byte of the output stream.
Applications
BT.656 output video generation
PAL & NTSC SDTV video format conversion
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Introduction |
ITU-R BT.656 video decoder |
By Quotes |
None |
300 MHz |
None |
|
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DEC_BT656 is a digital video decoder with integrated colour-space converter. It's function is to extract the valid pixels from a BT.656 video stream and convert them to 24-bit RGB for subsequent processing.
Pixels are extracted from the BT.656 input stream and converted to RGB888 format.
Application
BT.656 input video capture and processing
PAL & NTSC SDTV interlaced format conversion
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Introduction |
Color-space Converter |
By Quotes |
None |
400 MHz |
None |
|
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This IP is a fully pipelined color-space converter that converts pixels between the RGB and YCbCr color spaces. In total, the IP Core package contains two distinct modules – one module that converts from 24-bit RGB to 30-bit 4:4:4 YCbCr and the other that performs the reciprocal operation from 4:4:4 YCbCr to RGB.
Application
Digital video and image processing
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Introduction |
H.264 Encoder IP Core |
By Quotes |
None |
150 MHz |
None |
|
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This H.264 Encoder IP core has been developed to be the highest throughput standards compliant hardware H.264 video compressor.
The IP offers two encoder variants to meet the different targets of features.
The IP include 2 mode.
H264E-I: H.264 encoder compliant with CAVLC 4:4:4 Intra Profile (all frames are keyframes)
The IP core is smaller but yields less compression. It does not require external memory.
H264E-P: H.264 encoder compliant with High 4:4:4 Predictive Profile:
The IP core is larger but offers a significantly better compression.
Both share the same outstanding processing speed of more than 5.2 pixels encoded per cycle.
The data interfaces in the H.264 Encoder IP Core use the AXI industry standard.
The Master I/O data interfaces use an AXI3 bus, forward compatible with AXI4 interconnects.
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Introduction |
Digital Video Scaler |
By Quotes |
None |
250 MHz |
None |
|
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The IP Core is a studio quality video scaler capable of generating interpolated output images from 16 x 16 up to 216 x 216 pixels in resolution. The architecture permits seamless scaling (either up or down) depending on the chosen scale factor. Internally, the scaler uses a 24-bit accumulator and a bank of polyphase FIR filters with 16 phases or interpolation points. All filter coefficients are programmable, allowing the user to define a wide range of filter characteristics.
Pixels flow in and out of the video scaler in accordance with the valid-ready pipeline protocol. Pixels are transferred into the scaler on a rising clock-edge when pixin_val is high and pixin_rdy is high. As such, the pipeline protocol allows both input and output interfaces to be stalled independently.
The scaler is partitioned into a horizontal scaling module in series with a vertical scaling module .
Application
Support for the latest generation video formats with resolutions of 4K and above
Video scaling for flat panel displays, portable devices, video consoles, video format converters, set-top boxes, digital TV etc.
Conversion of all standard and custom video resolutions such as HD720P to HD1080P, XGA to VGA etc.
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Introduction |
Bilinear Video Scaling Engine |
By Quotes |
None |
250 MHz |
None |
|
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This IP is a very high quality video scaler capable of generating interpolated output images from 16x16 up to 216 x 216 pixels in resolution. The architecture permits seamless scaling (either up or down) depending on the chosen scale factor. Internally, the scaler uses a 24-bit accumulator and a bank of polyphase FIR filters with 16 phases or interpolation points. All filter coefficients are programmable, allowing the user to define a wide range of filter characteristics.
Pixels flow in and out of the scaling engine in accordance with the valid-ready pipeline protocol.As such, the pipeline protocol allows both input and output interfaces to be stalled independently.
The scaler is partitioned into a horizontal scaling section in series with avertical scaling section.
Application
Conversion of popular video formats to any other resolution such as VGA to XGA, SVGA to HD1080 etc.
Picture in Picture (PiP) applications
High quality 24-bit RGB/YCbCr video scaling
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Introduction |
Text Overlay Module |
By Quotes |
None |
200 MHz |
None |
|
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The IP Core is a highly versatile On Screen Display (OSD) module that allows text and bitmap graphics to be inserted over RGB video. The module supports a wide range of text effects and the
programming interface is very simple. Text is written to a 64x32 character buffer which is mapped (via a bitmap ROM) directly to the display.
The characters in the buffer are displayed in a 'TEXT BOX' which may be positioned anywhere in the video display area. Bitmaps for each character are stored in a ROM which may be modified to support different font styles or bitmap graphics.
Pixels and syncs flow in and out of the overlay module in accordance with the valid-ready pipeline protocol.
Application
Window movement in the same manner as a 2D 'BitBlt'
Terminal and Console windows
Low cost text and graphics applications
Digital TV and home-media solutions
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Introduction |
2D Graphics Overlay |
By Quotes |
None |
200 MHz |
None |
|
|
This is a highly versatile on-screen display that allows high-quality anti-aliased bitmap graphics to be inserted over RGB video. The module supports a wide range of graphics effects and the programming interface is very simple to use. The bitmap overlay is partitioned into an array of tiles which are addressed by means of an 8-bit value stored in a 64x64 tile buffer. There are four tile sizes available - either 8x8, 16x16, 32x32 or 64x64.
The tiles in the buffer are displayed in a graphics window which may be positioned anywhere within the display area. Bitmaps for each tile are stored in a user-defined ROM which can contain up to 256 different bitmaps stored over three bit-planes. Depending on the chosen graphics mode, the 3-bits per pixel may be used to select one colour from a palette of eight, eight levels of alpha transparency or seven colours on a transparent background.
Pixels and syncs flow in and out of the overlay module in accordance with the valid-ready pipeline protocol.
Application
Animated 2D graphics including hardware sprites, mouse pointers, cursors , parallax scrolling, moving banners etc.
Interactive guides, menus, tables, lists etc.
Digital TV and home-media solutions
Professional and functional 2D graphic displays and video overlays
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Introduction |
Digital Video overlay module |
By Quotes |
None |
250 MHz |
None |
|
|
This IP is a highly versatile video multiplexer that allows one video stream to be inserted over another. By cascading a series of video overlay modules together, any number of video sources may be multiplexed together. The module supports input video streams of any resolution or aspect ratio up to 216 x 216 pixels in size. Video overlay parameters may be changed on a frame-by-frame basis to dynamically change the size and position of the video overlay.
Pixels and syncs flow in and out of the video overlay module in accordance with the valid-ready pipeline protocol. The pipeline protocol allows both input and output interfaces to be stalled independently.
In addition, the overlay module supports a number of blending operations including an 8-bit alpha channel and bitwise AND, OR and XOR functions.
Application
Network and Tactical operations centres
Digital-video special effects
Broadcast TV and film production
CCTV and security camera systems
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Introduction |