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  • uIP： PLL 2000M UMC 28 nm logic and Mixed-Mode HPC process
  • uIP ID： 495339835
  • μIP Type： Analog μIP
  • HDL： Verilog Behavioral Model
  • Warranty： YES
  • Simulation Tool： Cadence NC-Verilog
  • Tool Version：
  • Design Format： GDS
  • Merge In Foundry： YES
    •
    Designer Information
  • Member ID：8972661000700018
  • Designer Rating：
  • Feedback received：0
 

1. Introduction：

A Phase-Locked Loop (PLL) circuit used to generate the high-speed clock with an operating frequency up to 2000 MHz.

This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process.

It can be integrated into a chip to generate an accurate clock. 


2. License Price：

By Quotes

Multiple License : NO


3. Trial Run Price：

By Quotes


4. Clock Rate：

2 GHz


5. Area：

230 μm^2


6. Technology：

28 nm


7. Version：

1