1. Introduction：

This JPEG Decoder IP core has been developed to be a complete standards compliant JPEG / MJPEG Hardware Decompressor / Decoder.

When decoding JPEG images, pixel throughput can not be fixed for compressed JPEGs of arbitrary quality, as it depends on the compression ratio (bits needed to encode one pixel).

To circumvent this limitation JPEG Decoder IP features a dual pixel component pipeline, allowing for greater decoding speeds.

 

2. License Price：

By Quotes

Multiple License : NO

3. Clock Rate：

250 MHz

4. Logic Gate Count：

None

5. Technology：

130 nm

6. Version：

1.0