1. Introduction：

The IP is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can also be used in any serial interface where timing and electrical specification can be satisfied.
This IP has four individual Transmitter (TX) and Receiver (RX) channels, and one common phase lock loop (PLL).

2. License Price：

By Quotes

Multiple License : NO

3. Trial Run Price：

By Quotes

4. Clock Rate：

25 MHz

5. Area：

2.295 μm^2

6. Technology：

65 nm

7. Version：

1.1