Needhelp
?
| Wide band 3Ghz-6GHz integer phase-locked loop | By Quotes | 1.080 M μm^2 | 6 GHz | 65 nm |  |
|
| It is an integer-N phase-locked loop frequency synthesizer (PLL) based on fully integrated wide band LC-VCO with range from 3 GHz to 6 GHz with good phase noise performance. IP technology: TSMC CMOS CRN65LP. | Introduction | |||||
| Wide band 3Ghz-6GHz fractional phase-locked loop | By Quotes | 1.100 M μm^2 | 6 GHz | 65 nm | |
|
| It is a phase-locked loop frequency synthesizer (PLL) with integer-N/fractional-N modes based on fully integrated wide band LC-VCO with range from 3 GHz to 6 GHz with good phase noise performance. IP technology: TSMC CMOS CRN65LP. | Introduction | |||||
| 20 to 300 MHz integer-N frequency synthesizer | By Quotes | 85.000 K μm^2 | 300 MHz | None | |
|
| It is an integer-N PLL frequency synthesizer that generates a 20MHz to 300MHz output clock. The IP block uses 8MHz to 16MHz reference clock at CKREF. Build-in reference frequency detector indicates when reference frequency is too low. IP technology: SilTerra CMOS18G. | Introduction | |||||
| PLL 3000M UMC 28 nm logic and Mixed-Mode HPC process | By Quotes | 92.400 K μm^2 | 27 MHz | 28 nm | |
|
| It generates a stable high-speed clock from an external slower reference clock signal. It integrates a Voltage-Controlled Oscillator (VCO), a Phase-Frequency Detector (PFD), a Low-Pass Filter (LPF), a 9-bit programmable loop divider, a 2-bit programmable pre-divider and associated support circuitry. This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process, and it supports an operating voltage ranging from 0.81 V to 0.99 V with an operating junction temperature ranging between -40 °C and 125 °C. It accepts FREF frequency ranging from 6 MHz to 27 MHz and generates the output frequency up to 3000 MHz. | Introduction | |||||
| PLL 2000M UMC 28 nm logic and Mixed-Mode HPC process | By Quotes | 230.000 μm^2 | 2 GHz | 28 nm | |
|
| A Phase-Locked Loop (PLL) circuit used to generate the high-speed clock with an operating frequency up to 2000 MHz. This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process. It can be integrated into a chip to generate an accurate clock. | Introduction | |||||
| PLL 1600M UMC 28 nm logic and Mixed-Mode HPC process | By Quotes | 270.000 μm^2 | 1.6 GHz | 28 nm | |
|
| A Phase-Locked Loop (PLL) with an operating frequency ranging from 200 MHz to 1600 MHz. This PLL is designed with the UMC 28 nm logic and Mixed-Mode HPC process. It can be integrated into a chip to generate a high-speed clock. The embedded divide-by-4 loop divider allows users to boost the output frequency of up to 1600 MHz. | Introduction | |||||
| PLL 800M UMC 28 nm logic and Mixed-Mode HPC process | By Quotes | 230.000 μm^2 | 800 MHz | 28 nm | |
|
| It is a 28-nm low-power spread spectrum clock generator that supports an operating frequency ranging from 400 MHz to 800 MHz and from 200 MHz to 400 MHz. This SSCG is programmable to perform the frequency synthesis and spread-spectrum function for the Electro Magnetic Interference (EMI) reduction in various ASIC designs. | Introduction | |||||
| PLL 1300M UMC 28 nm logic and Mixed-Mode HPC process | By Quotes | 109.850 K μm^2 | 50 MHz | 28 nm | |
|
| It is used to generate a stable, high-speed clock from an external slower clock signal. It integrates one Voltage-Controlled Oscillator (VCO), one Phase-Frequency Detector (PFD), one Low-Pass Filter (LPF), one 8-bit programmable divider, and other associated support circuitries. This PLL supports an operating voltage ranging from 0.81 V to 0.99 V with an operating junction temperature ranging between -40 °C and 125 °C. This IP uses the input operating frequency of PFD ranging from 6 MHz to 25 MHz and generates the output frequency ranging from 25 MHz to 1300 MHz. The jitter performance of a PLL is highly dependent on the floor plan of ASIC. Because PLL is a sensitive cell when integrated into an ASIC design, the best way to maximize its capacity is to keep PLL away from the noisy blocks in the core region, such as the memory block and the high-driving logic circuit, and the I/O region, such as the high-driving I/O. This PLL must be placed around the I/O area. Providing sufficient space between this PLL and the noisy blocks is a simple and effective approach to reduce the coupled substrate noise. | Introduction | |||||
| PLL with Multiple Output Frequency | By Quotes | 40.000 K μm^2 | 12.156 MHz | 130 nm | |
|
| The PLL is a 0.13μm Phase-Locked Loop (PLL) cell that provides a clock multiplier that can generate a stable 48M/96M/120MHz/156MHz clock from a 12MHz clock source. This is a “generic” PLL which integrates the Voltage-Controlled Oscillator (VCO), Phase-Frequency Detector, Low Pass Filter, Loop Divider and Post Divider. This PLL provides an operating voltage range of 1.08V ~ 1.32V, and an operating junction temperature range of -40˚ ~ 125℃. | Introduction | |||||
| 2.4G PLL(UMC 28nm HPC) | By Quotes | 24.000 K μm^2 | 2.4 GHz | 28 nm | |
|
| Clock output 2.4GHz Input clock 10 ~ 50MHz Current consumption: < 4mA Supply: 1.8V / 0.9V UMC 28nm HPC | Introduction | |||||
| μIP | Price | Logic Gate Count | Clock Rate | Technology | Ratings | |
|---|---|---|---|---|---|---|