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  • uIP： PLL with Multiple Output Frequency
  • uIP ID： 2021851027
  • μIP Type： Analog μIP
  • HDL： Verilog Behavioral Model
  • Warranty： YES
  • Simulation Tool： Cadence NC-Verilog
  • Tool Version：
  • Design Format： GDS & Schematic
  • Merge In Foundry： YES
    •
    Designer Information
  • Member ID：5141877000000300
  • Designer Rating：
  • Feedback received：0
 

1. Introduction：

 

The PLL is a 0.13μm Phase-Locked Loop (PLL) cell that provides a clock multiplier that can generate a stable 48M/96M/120MHz/156MHz clock from a 12MHz clock source.  This is a “generic” PLL which integrates the Voltage-Controlled Oscillator (VCO), Phase-Frequency Detector, Low Pass Filter, Loop Divider and Post Divider.   This PLL provides an operating voltage range of 1.08V ~ 1.32V, and an operating junction temperature range of -40˚ ~ 125℃. 

2. License Price：

By Quotes

Multiple License : YES

   - Discount for 2 ~ 5 license：5 %
   - Discount for 6 ~ 10 license：10 %
   - Discount for 11 ~ license：0 %

3. Trial Run Price：

By Quotes

4. Clock Rate：

12.156 MHz

5. Area：

40 K μm^2

6. Technology：

130 nm

7. Version：

1.0