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IP Mart


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  • uIP： 20 to 300 MHz integer-N frequency synthesizer
  • uIP ID： 1112719064
  • μIP Type： Analog μIP
  • HDL： Verilog Behavioral Model
  • Warranty： NO
  • Simulation Tool： None
  • Tool Version：
  • Design Format： GDS & Schematic
  • Merge In Foundry： NO
    •
    Designer Information
  • Member ID：2713484000700082
  • Designer Rating：
  • Feedback received：0
 

1. Introduction：

  • It is an integer-N PLL frequency synthesizer that generates a 20MHz to 300MHz output clock. The IP block uses 8MHz to 16MHz reference clock at CKREF. Build-in reference frequency detector indicates when reference frequency is too low.
  • IP technology: SilTerra CMOS18G.

2. License Price：

By Quotes

Multiple License : NO

3. Trial Run Price：

By Quotes

4. Clock Rate：

300 MHz

5. Area：

85 K μm^2

6. Technology：

None

7. Version：

1.0