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  • uIP: Wide band 3Ghz-6GHz fractional phase-locked loop
  • uIP ID: 1379231648
  • μIP Type: Analog μIP
  • HDL: Verilog Behavioral Model
  • Warranty: NO
  • Simulation Tool: None
  • Tool Version:
  • Design Format: GDS & Schematic
  • Merge In Foundry: NO
    Designer Information
  • Member ID:2713484000700082
  • Designer Rating:
  • Feedback received:0
 

1. Introduction:

  • It is a phase-locked loop frequency synthesizer (PLL) with integer-N/fractional-N modes based on fully integrated wide band LC-VCO with range from 3 GHz to 6 GHz with good phase noise performance. 
  • IP technology: TSMC CMOS CRN65LP.

2. License Price:

By Quotes

Multiple License : NO

3. Trial Run Price:

By Quotes

4. Clock Rate:

6 GHz

5. Area:

1.1 M μm^2

6. Technology:

65 nm

7. Version:

1.0