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  • uIP: 10-Bit 1MSPS Cyclic A/D Converter
  • uIP ID: 1415944739
  • μIP Type: Analog μIP
  • HDL: Verilog Behavioral Model
  • Warranty: YES
  • Simulation Tool: Cadence NC-Verilog
  • Tool Version:
  • Design Format: GDS & Schematic
  • Merge In Foundry: YES
    Designer Information
  • Member ID:5171824000400575
  • Designer Rating:
  • Feedback received:0
 

1. Introduction:

This IP is a 1MSPS , single supply , 10-bit analog-to-digital converter (ADC) that combines a low cost, high speed CMOS process and a novel architecture. It is a complete ADC with an on chip, high performance sample-and-hold amplifier and voltage reference. An external reference can be chosen to suit the dc accuracy and temperature drift requirements of the application. The device uses a cyclic architecture with digital error correction logic to guarantee no missing code over the full operating range.

The input of this ADC is highly flexible. A truly differential input structure allows for both single-ended and differential input interface of varying span. The sample-and-hold amplifier (SHA) is equally suited for multiplexed systems that switched full-scale voltage levels in successive channels as well as sampling single-channel inputs at frequencies up to and beyond the Nyquist rate of 500KHz.


2. License Price:

By Quotes

Multiple License : YES

   - Discount for 2 ~ 5 license:5 %
   - Discount for 6 ~ 10 license:10 %
   - Discount for 11 ~ license:0 %


3. Trial Run Price:

By Quotes


4. Clock Rate:

10.12 MHz


5. Area:

300 K μm^2


6. Technology:

250 nm


7. Version:

1.0