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IP Mart




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  • uIP: Sigma-Delta Stereo CODEC in 55nm
  • uIP ID: 1120090945
  • μIP Type: Analog μIP
  • HDL: Verilog Behavioral Model
  • Warranty: YES
  • Simulation Tool: Synopsys VCS
  • Tool Version:
  • Design Format: GDS
  • Merge In Foundry: YES
    Designer Information
  • Member ID:1130893000900598
  • Designer Rating:
  • Feedback received:0
 

1. Introduction:

The IP is a high resolution, single-chip stereo CODEC that employs the Sigma-Delta noise shaping technique for 55nm logic process. The ADC, DAC and power amplifier are integrated in it. With 18bit resolution for DAC and 18bit resolution for ADC, The IP is suitable for applications in consumer digital audio systems, automobile audio, multimedia and digital systems.


2. License Price:

By Quotes

Multiple License : YES

   - Discount for 2 ~ 5 license:0 %
   - Discount for 6 ~ 10 license:0 %
   - Discount for 11 ~ license:0 %


3. Trial Run Price:

By Quotes


4. Clock Rate:

96 KHz


5. Area:

562.8 K μm^2


6. Technology:

55 nm


7. Version:

1.2