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| Motion-adaptive Video Deinterlacer | By Quotes | None | 200 MHz | None |  |
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| The IP Core is a studio quality 24-bit RGB video deinterlacer capable of generating progressive output video at any resolution up to 216 x 216 pixels. The design is fully programmable and supports any desired interlaced video format. The design allows for three possible deinterlacing schemes. These are: weave, bilinear interpolation or motion-adaptive interpolation. The weave approach applies no filtering and may be useful to obtain a 'raw' interlaced format for subsequent processing. The other two methods are classed as 'inter-field' interpolation methods as spatial filtering is performed between both odd and even fields to achieve a clean and progressive output. The relative merits and disadvantages of each scheme are discussed further into the document. The deinterlacer core features a fully integrated video frame buffer. This buffer is completely 'elastic' and will dynamically skip and/or repeat frames depending on the input and output frame rates. All frame buffer management is handled internally with the provision of a simple memory interface for storing odd and even fields off-chip. The memory interface is 128-bits wide and is completely generic. All memory transfers are sequential bursts of N x 128-bit words and may be adapted for connection to a variety of memory types such as SDRAM, DDR2 or DDR3. Application Digital TV set-top boxes. Industrial imaging. Automotive, home and personal media solutions Conversion of 'legacy' SDTV formats to HDTV video formats Generating progressive RGB video via inexpensive PAL/NTSC decoder chips Studio-quality video de-interlacing | Introduction | |||||
| Video Interlacer | By Quotes | None | 500 MHz | None | |
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| The IP Core is a fully pipelined video interlacer solution that converts any progressive video format into it's interlaced equivalent. Each interlaced output field will have half the number of lines as an input frame. The input and output interfaces are streaming interfaces that follow a simple valid-ready pipeline protocol. Input pixels and syncs are sampled on the rising edge of clk when P_VALID and P_READY are both high. Likewise, output pixels and syncs are sampled on the rising edge of clk when PO_VAL and PO_READY are high. Note that if no flow control is required in the design and the output is guaranteed to accept pixels without stalling, then the signal PO_READY may be tied high and the signal P_READY may be ignored. Application Video solutions for flat panel displays, portable devices, video consoles, video format converters, set-top boxes, digital TV etc. Conversion of all standard and custom video formats such as 1920x1080p to 1920x1080i, 720x480p to 720x480i etc. | Introduction | |||||
| Multi-format Video Deinterlacer | By Quotes | None | 200 MHz | None | |
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| The IP Core is a high quality 24-bit RGB video deinterlacer capable of generating progressive output video at up to 4096x4096 pixels in resolution. The design is fully customizable, supporting any desired interlaced video format. The deinterlacer allows for three possible filter algorithms - either BOB, ELA or LCI. All three methods are 'intra-field' methods that perform spatial filtering within the same field. For this reason, the output video is not subject to combing or tearing which is characteristic of a traditional 'weave' approach. Each algorithm has it relative merits in terms of image quality and hardware complexity. In particular, the enhanced LCI algorithm provides excellent all-round performance with reduced image softening and crisp clean edges. Application Conversion of 'legacy' SDTV formats to HDTV video formats Generating progressive RGB video via inexpensive PAL/NTSC decoder chips High-quality video de-interlacing without the overhead of a frame buffer Digital TV set-top boxes and home media solutions | Introduction | |||||
| Chroma Resampler | By Quotes | None | 400 MHz | None | |
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| The IP Core is a fully pipelined chroma resampler that converts pixels between 4:4:4 and 4:2:2 formats in the YCbCr colour space. In total, the IP Core package contains two distinct modules – one module that converts from 4:4:4 to 4:2:2 and the other that performs the reciprocal operation from 4:2:2 to 4:4:4. Pixels flow into the design in accordance with the valid ready pipeline protocol. Input pixels and syncs are sampled on the rising edge of clk when PIX_VALID and PIX_READY are both high. At the output interface, pixels and syncs are sampled on a the rising edge of clk when POUT_VALID and POUT_READY are high. The input and output sync signals are coincident with the first pixel of a frame and the first pixel of a line. These are useful to identify the video frame and line boundaries. Application Digital video and image processing Interfacing between different video processing and video transceiver ICs that use different colour formats | Introduction | |||||
| 0.13um Real Time Clock | By Quotes | None | 32 KHz | 130 nm | |
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| The RTC is a 0.13μm Real-Time-Clock cell that provides multiple clocks. This RTC provides an operating voltage range of 2.7V ~ 3.3V, and an operating junction temperature range of -40˚ ~ 125℃. | Introduction | |||||
| Cold Wallet Total solution | By Quotes | None | 200 MHz | None | |
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| This Cold Wallet Total solution can decrease timing for developing. Single chip solution. Include software solution for Bitcoin transaction. Secure Element 32 bit MCU Crypto Engine Hardware DSE USB2.0 device CRC calculation unit Application : Cold Wallet | Introduction | |||||
| 300 mA Capless LDO in 180 nm (VLDS0300RNM180) | By Quotes | None | None | 180 nm | |
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| Noise Quencher® Capless LDO (Silicon-proven 180 nm, 300 mA, excellent supply noise rejection and fast settling) Noise Quencher® LDOs: This series of low-power, fully-integrated low dropout (LDO) voltage regulators uses our patented Noise Quencher® Technology to provide best-in-class dynamic performance and noise rejection. The IP cores are unconditionally stable across a wide range of load currents and load capacitances and also do not require external components, thus saving package pins and valuable PC board space. These LDOs are optimized for stand-alone power management integrated circuit (PMIC) ASSPs and other analog and digital applications. | Introduction | |||||
| 300 mA Capless LDO in 130 nm (VLDS0300LS130) | By Quotes | None | None | 130 nm | |
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| Power Quencher® Capless LDO (Silicon-proven 130 nm, 300 mA, excellent quiescent current and load transient regulation) The Power Quencher® series of fully-integrated low dropout (LDO) voltage regulators operates with ultra-low levels of power consumption without sacrificing other areas of performance. They achieve a low-noise output voltage and do not require the external output capacitor that is typically needed in an LDO for loop stability and noise reduction. This saves component count, board space and cost, and improves overall system reliability. The Power Quencher® LDO voltage regulator IP cores are optimized for integration into Application Specific Integrated Circuits (ASICs) or Systems-on-a-Chip (SoCs), including radio frequency (RF), wireless, and Internet of Things (IoT) applications. | Introduction | |||||
| 400 mA Buck DC-DC Converter in 110 nm (VBKS0400T110) | By Quotes | None | None | 110 nm | |
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| Buck DC-DC Converter (Silicon-proven 110 nm, 400mA, excellent efficiency) The VBKS0400T110 IP core is a Buck DC-DC switching converter that delivers up to 400 mA of load current. It includes voltage, current and clock references, power-on-reset circuitry, overcurrent protection, a temperature sensor and ESD protection. Soft-start circuitry prevents high currents during start-up, and soft-stop circuitry provides a controlled shut-down sequence during a sudden shut down or fault detection. | Introduction | |||||
| 140 mA Buck DC-DC Converter in 40 nm (VBKS0140T040) | By Quotes | None | None | 40 nm | |
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| Buck DC-DC Converter for Integrated PMU (Silicon-proven 40 nm, 140 mA, optimized clocking to eliminate spurious emissions for low system noise) This series of buck DC-DC converters delivers up to 140 mA of load current and features optimized clocking options to eliminate spurious emissions resulting in much lower system noise. This buck DC-DC converter is silicon-proven in a 40 nm process and is a part of our 40 nm integrated power management unit (PMU) IP core series that has been optimized for integration into Application Specific Integrated Circuits (ASICs) or Systems-on-a-Chip (SoCs), including radio frequency (RF), wireless, and narrowband Internet of Things (NB-IoT) applications. | Introduction | |||||
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