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| PLL 3000M UMC 28 nm logic and Mixed-Mode HPC process | By Quotes | 92.400 K μm^2 | 27 MHz | 28 nm |  |
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| It generates a stable high-speed clock from an external slower reference clock signal. It integrates a Voltage-Controlled Oscillator (VCO), a Phase-Frequency Detector (PFD), a Low-Pass Filter (LPF), a 9-bit programmable loop divider, a 2-bit programmable pre-divider and associated support circuitry. This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process, and it supports an operating voltage ranging from 0.81 V to 0.99 V with an operating junction temperature ranging between -40 °C and 125 °C. It accepts FREF frequency ranging from 6 MHz to 27 MHz and generates the output frequency up to 3000 MHz. | Introduction | |||||
| BOSCH CAN 2.0A/B AND CAN FD 1.0 CONTROLLER | By Quotes | None | None | None | |
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| The CAN controller is an I2C/APB compliant controller to act as a transmitter or receiver in the CAN bus. | Introduction | |||||
| CAN 2.0 & CAN FD Bus Controller Core | By Quotes | 12.000 K Gates | None | None | |
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| The CAN protocol uses a multi-master bus configuration for the transfer of frames be- tween nodes of the network and manages error handling with no burden on the host processor. The core enables the user to set up economic and reliable links between vari- ous components. It appears as a memory-mapped I/O device to the host processor, which accesses the CAN core to control the transmission or reception of frames. The CAN core is easy to use and integrate, featuring programmable interrupts, data and baud rates; a configurable number of independently programmable acceptance filters; and a generic processor interface or optionally an AMBA APB, or AHB-Lite interface. It imple- ments a flexible buffering scheme, allowing fine-tuning of the core size to satisfy the requirements of each specific application | Introduction | |||||
| Octal SPI Master/Slave Controller | By Quotes | 4.641 K Gates | 500 MHz | None | |
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| Designed to work with a wide variety of SPI bus variants, the core supports run-time control of several SPI protocol parameters. For example, the SPI frame width can be 1 to 4 bytes, the most significant bit position in a frame, serial clock phase and polarity are all software- programmable. In master mode the core can control up to 32 slaves. A software controllable clock generator derives the serial clock for master mode, by dividing the frequency of a clock line dedicated for that purpose | Introduction | |||||
| USB 2.0 ON-THE-GO CONTROLLER | By Quotes | 75.000 K Gates | 200 MHz | None | |
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| This is a universal serial bus (USB) 2.0 On-The-Go (OTG) Controller, which can play dual-role, as a host or a device controller. When it acts as a host, it contains a USB host controller to support all speed transactions. | Introduction | |||||
| USB 3.1 GEN1 DUAL-ROLE CONTROLLER | By Quotes | None | 30 MHz | None | |
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| This is an USB 3.1 Gen1 dual-role controller, which is compliant to USB 2.0/USB 3.1 Gen1 specifications. The controller can act as a standard host or peripheral for easy system implementation. The role can be selected via static pin selection. | Introduction | |||||
| RC Oscillator | By Quotes | 0.970 μm^2 | 10.2 Hz | 3 nm | |
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| The digitally controlled RC oscillators optimized for ultra low power applications. Application: • Hand held devices • Wireless Power devices • Battery powered stand-by devices | Introduction | |||||
| MIPI PHY | By Quotes | None | None | None | |
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| This product offers complete debug facilities to validate Application processors with MIPI interfaces, MIPI Cameras and MIPI displays. | Introduction | |||||
| Bluetooth 5.2 Dual | By Quotes | None | None | 22 nm | |
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| This bluebooth is of the lowest power consumption. | Introduction | |||||
| Bluetooth 5.2 | By Quotes | None | None | 22 nm | |
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| It's ultra-low-power RF transceiver IP and is designed to meet 2.4 GHz standards. | Introduction | |||||
| μIP | Price | Logic Gate Count | Clock Rate | Technology | Ratings | |
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