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| Rapid IO PHY in 65nm | By Quotes | 2.295 μm^2 | 25 MHz | 65 nm |  |
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| The IP is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can also be used in any serial interface where timing and electrical specification can be satisfied. This IP has four individual Transmitter (TX) and Receiver (RX) channels, and one common phase lock loop (PLL). | Introduction | |||||
| USB 3.0 PHY in 110nm | By Quotes | 1.000 M μm^2 | 25 MHz | 110 nm | |
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| The IP is a high speed SERDES macro which complies with USB3.0 electrical interface specification. This macro can be easily fabricated to form multiple lanes and implemented in USB systems design, both Host and Device.The IP is supported USB3.0 Super Speed (5Gbps) protocol and data rate. | Introduction | |||||
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