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| 12-Bit 800KSPS Low Power SAR-ADC | By Quotes | None | 25 MHz | 180 nm |  |
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| The SAR-ADC is a low power ADC that is implemented in Successive Approximation architecture. It can provide 12-bit resolution capability with only 3V supply voltage. It accepts an analog input range from 0 to VCC and digitizes the input at a maximum sampling frequency rate of 800KHz at 5V supply voltage. This ADC also includes MUX design to select 0 of 7 analog inputs. The power dissipation is less than 5mW with 5V power supply. This SAR-ADC is implemented in SMIC 0.18μm generic CMOS technology. | Introduction | |||||
| Rapid IO PHY in 65nm | By Quotes | 2.295 μm^2 | 25 MHz | 65 nm | |
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| The IP is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can also be used in any serial interface where timing and electrical specification can be satisfied. This IP has four individual Transmitter (TX) and Receiver (RX) channels, and one common phase lock loop (PLL). | Introduction | |||||
| USB 3.0 PHY in 110nm | By Quotes | 1.000 M μm^2 | 25 MHz | 110 nm | |
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| The IP is a high speed SERDES macro which complies with USB3.0 electrical interface specification. This macro can be easily fabricated to form multiple lanes and implemented in USB systems design, both Host and Device.The IP is supported USB3.0 Super Speed (5Gbps) protocol and data rate. | Introduction | |||||
| PCI Express Gen4 PHY IP in TSMC 12nm FFC | By Quotes | None | 25 MHz | 12 nm | |
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| The Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE v4.4 inter- face spec. Lower power consumption is achieved due to support of addition- al PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption. | Introduction | |||||
| PCI Express Gen4 PHY IP in 28nm HPC+ | By Quotes | None | 25 MHz | 28 nm | |
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| The Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE v4.4 inter- face spec. Lower power consumption is achieved due to support of addition- al PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption. | Introduction | |||||
| DSP-BASED ETHERNET TRANSCEIVER in UMC 28nm HPC+ | By Quotes | None | 25 MHz | 28 nm | |
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| A 28nm DPS-based Gigabit Ethernet transceiver. Highly intergrated 1000BASE-T, 100BASE-TX, 100BASE-FX and 10BASE-Te. Fully compliant with 100BASE-FX IEEE 802.2u standard | Introduction | |||||
| PLL 3000M UMC 28 nm logic and Mixed-Mode HPC process | By Quotes | 92.400 K μm^2 | 27 MHz | 28 nm | |
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| It generates a stable high-speed clock from an external slower reference clock signal. It integrates a Voltage-Controlled Oscillator (VCO), a Phase-Frequency Detector (PFD), a Low-Pass Filter (LPF), a 9-bit programmable loop divider, a 2-bit programmable pre-divider and associated support circuitry. This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process, and it supports an operating voltage ranging from 0.81 V to 0.99 V with an operating junction temperature ranging between -40 °C and 125 °C. It accepts FREF frequency ranging from 6 MHz to 27 MHz and generates the output frequency up to 3000 MHz. | Introduction | |||||
| USB2.0 OTG PHY in 40 nm | 80000 Points | 257.556 K μm^2 | 30.6 MHz | 40 nm | |
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| The IP is an UTMI+ Level 3 compatible USB2.0 OTG function transceiver IP. It is comprised of both USB1.1 and USB2.0 transceivers; itis comprised of digital logic needed to convert USB serial data to 8 or 16 bit parallel data for high speed and full speed. It is also support full speed and low speed serial mode. | Introduction | |||||
| USB2.0 UTMI Device PHY(non-oscillator) | 100000 Points | 280.000 K μm^2 | 30.6 MHz | 40 nm | |
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| The USB PHY is an UTMI compatible USB2.0 device PHY IP which does not require external oscillator reference. It is comprised of both USB1.1 and USB2.0 transceivers and it is also comprised of digital logic needed to convert USB serial data to 8 or 16 bit parallel data. | Introduction | |||||
| 12-Bit 50 MSPS ADC in IBM 180 SOI | By Quotes | 280.000 μm^2 | 50 MHz | 180 nm | |
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| MICIP_ADC12 is compact and low power 12-bit analog-to-digital converter silicon IP. This ADC uses 1.5b/stage pipelined architecture optimized for low power and small area. | Introduction | |||||
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