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| Bluetooth 5.2 Dual | By Quotes | None | None | 22 nm |  |
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| This bluebooth is of the lowest power consumption. | Introduction | |||||
| Bluetooth 5.2 | By Quotes | None | None | 22 nm | |
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| It's ultra-low-power RF transceiver IP and is designed to meet 2.4 GHz standards. | Introduction | |||||
| Power Controller | By Quotes | 0.165 μm^2 | None | 90 nm | |
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| It is a configurable core that is configured for each specific SoC, delivering all the necessary auxiliary supply, monitoring and protection. | Introduction | |||||
| RC Oscillator | By Quotes | 0.970 μm^2 | 10.2 Hz | 3 nm | |
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| The digitally controlled RC oscillators optimized for ultra low power applications. Application: • Hand held devices • Wireless Power devices • Battery powered stand-by devices | Introduction | |||||
| Rapid IO PHY in 65nm | By Quotes | 2.295 μm^2 | 25 MHz | 65 nm | |
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| The IP is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can also be used in any serial interface where timing and electrical specification can be satisfied. This IP has four individual Transmitter (TX) and Receiver (RX) channels, and one common phase lock loop (PLL). | Introduction | |||||
| Low power oscillator | 12000 Points | 100.100 μm^2 | 32 KHz | 40 nm | |
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| OSC32K is designed for 40nm advance process with 1.2v to 3.3v wide power(VDD) range. | Introduction | |||||
| PLL 800M UMC 28 nm logic and Mixed-Mode HPC process | By Quotes | 230.000 μm^2 | 800 MHz | 28 nm | |
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| It is a 28-nm low-power spread spectrum clock generator that supports an operating frequency ranging from 400 MHz to 800 MHz and from 200 MHz to 400 MHz. This SSCG is programmable to perform the frequency synthesis and spread-spectrum function for the Electro Magnetic Interference (EMI) reduction in various ASIC designs. | Introduction | |||||
| PLL 2000M UMC 28 nm logic and Mixed-Mode HPC process | By Quotes | 230.000 μm^2 | 2 GHz | 28 nm | |
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| A Phase-Locked Loop (PLL) circuit used to generate the high-speed clock with an operating frequency up to 2000 MHz. This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process. It can be integrated into a chip to generate an accurate clock. | Introduction | |||||
| PLL 1600M UMC 28 nm logic and Mixed-Mode HPC process | By Quotes | 270.000 μm^2 | 1.6 GHz | 28 nm | |
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| A Phase-Locked Loop (PLL) with an operating frequency ranging from 200 MHz to 1600 MHz. This PLL is designed with the UMC 28 nm logic and Mixed-Mode HPC process. It can be integrated into a chip to generate a high-speed clock. The embedded divide-by-4 loop divider allows users to boost the output frequency of up to 1600 MHz. | Introduction | |||||
| 12-Bit 50 MSPS ADC in IBM 180 SOI | By Quotes | 280.000 μm^2 | 50 MHz | 180 nm | |
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| MICIP_ADC12 is compact and low power 12-bit analog-to-digital converter silicon IP. This ADC uses 1.5b/stage pipelined architecture optimized for low power and small area. | Introduction | |||||
| μIP | Price | Logic Gate Count | Clock Rate | Technology | Ratings | |
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