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Triple 10-bit 330 MSPS Video DAC IP in TSMC 90 nm By Quotes 330.000 μm^2 330 MHz 90 nm  
MIC_DAC10X3 is a 10-bit Triple DAC designed in TSMC 90 nm logic process. It consists of a current steering DAC. The DAC uses a fully differential architecture. The input data of the DAC is in 1.2 V, in unsigned format. Introduction
Dual-Channel 12-bit 80 MSPS ADC IP in UMC 65 nm By Quotes 450.000 μm^2 0.8 MHz 65 nm  
ADC X is an ultra-compact and very low power analog-to-digital converter (ADC) IP. The 12-bit 80 MSPS Dual ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. IP architecture is robust and can be ported to other 65 nm processes.The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. Introduction
12-Bit 800KSPS Low Power SAR-ADC By Quotes None 25 MHz 180 nm  
The SAR-ADC is a low power ADC that is implemented in Successive Approximation architecture. It can provide 12-bit resolution capability with only 3V supply voltage. It accepts an analog input range from 0 to VCC   and digitizes the input at a maximum sampling frequency rate of 800KHz at 5V supply voltage. This ADC also includes MUX design to select 0 of 7 analog inputs. The power dissipation is less than 5mW with 5V power supply. This SAR-ADC is implemented in SMIC 0.18μm generic CMOS technology. Introduction
2.4G PLL(UMC 28nm HPC) By Quotes 24.000 K μm^2 2.4 GHz 28 nm  
Clock output 2.4GHz Input clock 10 ~ 50MHz Current consumption: < 4mA Supply: 1.8V / 0.9V UMC 28nm HPC Introduction
14-Bit 3 MSPS ADC in GSMC110nm 60000 Points 32.000 K μm^2 3 MHz 110 nm  
UIP_ADC14_3M_245303  is  compact  and  low power 14-bit analog-to-digital converter silicon IP.  It  has  20  single-end  input  channel selection  multiplexer  or  10  differential  input channels  selection.  This  ADC  uses  fully differential SAR architecture optimized for low power and small area. The ADC is designed for  high  dynamic  performance  for  input frequencies  up  to  Nyquist  rate.  This  ADC consumes  150  uA  at  3  MSPS  operation  and occupies  silicon  area  of  0.32 mm2 .  The  ADC has  high  immunity  to  substrate  noise  and  is ideal  for  SoC  integration.   APPLICATIONS  General purpose data acquisition Battery monitory system  Temperature monitory system Introduction
4.2V-to-1.2V DC/DC Converter By Quotes 40.000 K μm^2 1 MHz 130 nm  
The DCDC12 is a 0.13μm DC to DC converter in buck mode cell that converters input voltage to a smaller output voltage. The output voltage can be programmed from 1.05V to 1.3V.An external 10uH inductor is necessary. Introduction
4.2V-to-1.8V DC/DC Converter By Quotes 40.000 K μm^2 1 Hz 130 nm  
  The DCDC18 is a 0.13μm DC to DC converter in buck mode cell that converters input voltage to a smaller output voltage. The output voltage can be programmed from 1.65V to 1.9V.An external 10uH inductor is necessary.  Introduction
PLL with Multiple Output Frequency By Quotes 40.000 K μm^2 12.156 MHz 130 nm  
  The PLL is a 0.13μm Phase-Locked Loop (PLL) cell that provides a clock multiplier that can generate a stable 48M/96M/120MHz/156MHz clock from a 12MHz clock source.  This is a “generic” PLL which integrates the Voltage-Controlled Oscillator (VCO), Phase-Frequency Detector, Low Pass Filter, Loop Divider and Post Divider.   This PLL provides an operating voltage range of 1.08V ~ 1.32V, and an operating junction temperature range of -40˚ ~ 125℃.  Introduction
10-bit 165 MSPS ADC IP in 28 nm 80000 Points 70.000 K μm^2 165 MHz 28 nm  
UIP_ADC10_165M_564144 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs.   The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances.   The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 12mW at 165 MSPS operation and requires silicon area of 0.07 mm^2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format.   UIP_ADC10_165M_564144 can be used in the following applications:   ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel Introduction
10-bit 165 MSPS ADC IP in 28 nm 80000 Points 70.000 K μm^2 165 MHz 28 nm  
UIP_ADC10_165M_809744 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs.   The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances.   The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 12mW at 165 MSPS operation and requires silicon area of 0.07 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format.   UIP_ADC10_165M_809744 can be used in the following applications:   ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel ‧IOT Introduction
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