Needhelp
?
| 12-Bit 320MSPS IQ DAC in IBM SOI 180nm | By Quotes | 254.000 K μm^2 | 320 MHz | 180 nm |  |
|
| MIC_DAC12X2 is compact and low power 12-bit digital-to-analog converter silicon IP in IBM 180nm SOI process. It features two channel current steering DAC. | Introduction | |||||
| USB2.0 OTG PHY in 40 nm | 80000 Points | 257.556 K μm^2 | 30.6 MHz | 40 nm | |
|
| The IP is an UTMI+ Level 3 compatible USB2.0 OTG function transceiver IP. It is comprised of both USB1.1 and USB2.0 transceivers; itis comprised of digital logic needed to convert USB serial data to 8 or 16 bit parallel data for high speed and full speed. It is also support full speed and low speed serial mode. | Introduction | |||||
| USB2.0 UTMI Device PHY(non-oscillator) | 100000 Points | 280.000 K μm^2 | 30.6 MHz | 40 nm | |
|
| The USB PHY is an UTMI compatible USB2.0 device PHY IP which does not require external oscillator reference. It is comprised of both USB1.1 and USB2.0 transceivers and it is also comprised of digital logic needed to convert USB serial data to 8 or 16 bit parallel data. | Introduction | |||||
| 8-Bit 7 GSPS SAR ADC | By Quotes | 300.000 K μm^2 | 7 GHz | 16 nm | |
|
| This IP is compact and low power 8-bit Time interleaved SAR analog-to-digital converter silicon IP.This ADC uses fully differential SAR architecture optimized for low power and small silicon area. APPLICATIONS Serdes Receiver Coherent Transceivers Data acquisition | Introduction | |||||
| 10-Bit 1MSPS Cyclic A/D Converter | By Quotes | 300.000 K μm^2 | 10.12 MHz | 250 nm | |
|
| This IP is a 1MSPS , single supply , 10-bit analog-to-digital converter (ADC) that combines a low cost, high speed CMOS process and a novel architecture. It is a complete ADC with an on chip, high performance sample-and-hold amplifier and voltage reference. An external reference can be chosen to suit the dc accuracy and temperature drift requirements of the application. The device uses a cyclic architecture with digital error correction logic to guarantee no missing code over the full operating range. The input of this ADC is highly flexible. A truly differential input structure allows for both single-ended and differential input interface of varying span. The sample-and-hold amplifier (SHA) is equally suited for multiplexed systems that switched full-scale voltage levels in successive channels as well as sampling single-channel inputs at frequencies up to and beyond the Nyquist rate of 500KHz. | Introduction | |||||
| 14-Bit 3 MSPS ADC in GSMC110nm | By Quotes | 322.000 K μm^2 | 3 MHz | 110 nm | |
|
| MCR_GS110_ADC14 is compact and low power 14-bit analog-to-digital converter silicon IP. It has 20 single-end input channel selection multiplexer or 10 differential input channels selection. This ADC uses fully differential SAR architecture optimized for low The ADC is designed for high dynamic performance for input frequencies up to Nyquist rate. | Introduction | |||||
| Sigma-Delta Stereo CODEC in 55nm | By Quotes | 562.800 K μm^2 | 96 KHz | 55 nm | |
|
| The IP is a high resolution, single-chip stereo CODEC that employs the Sigma-Delta noise shaping technique for 55nm logic process. The ADC, DAC and power amplifier are integrated in it. With 18bit resolution for DAC and 18bit resolution for ADC, The IP is suitable for applications in consumer digital audio systems, automobile audio, multimedia and digital systems. | Introduction | |||||
| USB 3.0 PHY in 110nm | By Quotes | 1.000 M μm^2 | 25 MHz | 110 nm | |
|
| The IP is a high speed SERDES macro which complies with USB3.0 electrical interface specification. This macro can be easily fabricated to form multiple lanes and implemented in USB systems design, both Host and Device.The IP is supported USB3.0 Super Speed (5Gbps) protocol and data rate. | Introduction | |||||
| μIP | Price | Logic Gate Count | Clock Rate | Technology | Ratings | |
|---|---|---|---|---|---|---|