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| USB 3.1 GEN1 DUAL-ROLE CONTROLLER | By Quotes | None | 30 MHz | None |  |
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| This is an USB 3.1 Gen1 dual-role controller, which is compliant to USB 2.0/USB 3.1 Gen1 specifications. The controller can act as a standard host or peripheral for easy system implementation. The role can be selected via static pin selection. | Introduction | |||||
| MIPI PHY | By Quotes | None | None | None | |
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| This product offers complete debug facilities to validate Application processors with MIPI interfaces, MIPI Cameras and MIPI displays. | Introduction | |||||
| RC Oscillator | By Quotes | 0.970 μm^2 | 10.2 Hz | 3 nm | |
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| The digitally controlled RC oscillators optimized for ultra low power applications. Application: • Hand held devices • Wireless Power devices • Battery powered stand-by devices | Introduction | |||||
| MIPI M-PHY Gear 4 IP in TSMC 12nm FFC | By Quotes | None | 11 GHz | 12 nm | |
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| MIPI M-PHY Gear 4 IP is compliant with the latest MIPI. Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification. A serial interface technology with high bandwidth capabilities and supports HS Gear4 rates up to 11.6Gbps, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. The MIPI M-PHY Gear 4 IP compliant to the RMMI interface which allows UniPro controller and UFS Controller. | Introduction | |||||
| PCI Express Gen4 PHY IP in TSMC 12nm FFC | By Quotes | None | 25 MHz | 12 nm | |
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| The Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE v4.4 inter- face spec. Lower power consumption is achieved due to support of addition- al PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption. | Introduction | |||||
| 8-Bit 7 GSPS SAR ADC | By Quotes | 300.000 K μm^2 | 7 GHz | 16 nm | |
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| This IP is compact and low power 8-bit Time interleaved SAR analog-to-digital converter silicon IP.This ADC uses fully differential SAR architecture optimized for low power and small silicon area. APPLICATIONS Serdes Receiver Coherent Transceivers Data acquisition | Introduction | |||||
| Bluetooth 5.2 Dual | By Quotes | None | None | 22 nm | |
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| This bluebooth is of the lowest power consumption. | Introduction | |||||
| Bluetooth 5.2 | By Quotes | None | None | 22 nm | |
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| It's ultra-low-power RF transceiver IP and is designed to meet 2.4 GHz standards. | Introduction | |||||
| 10-bit 165 MSPS ADC IP in 28 nm | 80000 Points | 70.000 K μm^2 | 165 MHz | 28 nm | |
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| UIP_ADC10_165M_564144 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances. The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 12mW at 165 MSPS operation and requires silicon area of 0.07 mm^2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format. UIP_ADC10_165M_564144 can be used in the following applications: ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel | Introduction | |||||
| 10-bit 165 MSPS ADC IP in 28 nm | 80000 Points | 70.000 K μm^2 | 165 MHz | 28 nm | |
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| UIP_ADC10_165M_809744 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances. The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 12mW at 165 MSPS operation and requires silicon area of 0.07 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format. UIP_ADC10_165M_809744 can be used in the following applications: ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel ‧IOT | Introduction | |||||
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