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| N-channel multiplexed FIR filter | By Quotes | None | 500 MHz | None |  |
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| The IP is an N-channel multiplexed FIR filter designed for high sample rate applications where hardware resources are limited. The main filter core is organized as a scalable systolic array permitting the user to specify large order filters without compromising maximum attainable clock-speed. Essentially the filter functions as if it were 'N' separate FIR filters. Each input sample is multiplexed into the filter at a sample rate equal to Fs /N, where Fs is the sampling frequency of the main filter core. Likewise, output samples are updated at a frequency of Fs /N. The first sample into the filter is aligned by asserting the signal X_VALID high. The signal Y_VALID_val is asserted with the first valid output sample. Data samples are advanced in the pipeline on the rising clock-edge of clk when en is active high. When en is low then all data samples are stalled. The clock-enable signal may be used to temporarily disable the filter - or possibly to modify the effective sampling frequency of the system clock. If the clock-enable is not needed it is recommended that this signal be tied high as it will improve overall circuit performance. Application Dual-channel inputs such as complex valued I/Q in digital communications systems High-speed filtering applications where hardware resources are limited General purpose FIR filters with odd or even numbers of taps | Introduction | |||||
| FIR filter | By Quotes | None | 300 MHz | None | |
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| FIR_F is an FIR filter implementation designed for very high sample rate applications. Organized as a systolic array the filter is modular and fully scalable, permitting the user to specify large order filters without compromising maximum attainable clock-speed. Mathematically, the filter implements the difference equation: y[n] = h0 x[n] + h1 x[n−1] + ... + hN x[n−N ] In the above equation, the input signal is x[n], the output signal is y[n] and h0 to hN represent the filter coefficients. The number N is the filter order, the number of filter taps being equal to N+1. Application General purpose FIR filters with odd or even numbers of taps Filters with arbitrary sets of coefficients Very high-speed filtering applications | Introduction | |||||
| Digital Down Converter with configurable Decimation Filter | By Quotes | None | 250 MHz | None | |
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| DDC is a complex-valued digital down-converter with a configurable number of decimation stages. The design is ideal for high sample-rate applications and permits a digital input signal to be mixed- down and re-sampled at a lower data rate. The DDC is suitable for the down-conversion of any digitally modulated signal to baseband – an essential step before digital processing. The DDC features a high-precision 16-bit DDS oscillator for the digital mixing stage. This oscillator is fully programmable and offers excellent phase and frequency resolution. The digital mixing stage is a complex multiplier that allows the mixing of both real and imaginary (I/Q) inputs. If only real inputs are required, then the imaginary input (q_in) should be tied low. The output decimation stage features a configurable decimate-by-2N poly-phase filter for both I and Q channels. Each filter stage is highly optimized to use only 12 multipliers while still achieving 80 dB of stop-band attenuation. Application Compatible with any digital modulation scheme - e.g. QPSK, BPSK, QAM, WiMAX, WCDMA, COFDM etc. Conversion of IF signals to baseband frequencies for subsequent processing Digital I/Q Demodulators | Introduction | |||||
| Binary PSK Demodulator | By Quotes | None | 200 MHz | None | |
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| IP is a Binary-PSK demodulator based on a multiply-filter-divide architecture. The design is robust and flexible and allows easy connectivity to an external ADC. As the the carrier recovery circuit is open-loop, there is no feedback path or loop-filter to configure. This results in an extremely simple circuit with a very fast carrier acquisition time. The only requirement is that the user set the desired symbol period and a suitable threshold level for the bit decisions at the symbol decoder. The other design parameters including carrier frequency, symbol rate and sampling frequency should be specified by the user before delivery of the IP Core 1 . The input data samples are 16-bit signed (2's complement) values that are synchronous with the system clock. Input values are sampled on the rising edge of clk when en is high. Application Robust, low bandwidth RF applications for small FPGA devices SRD and ISM band devices Medium to long-range telemetry Software radio | Introduction | |||||
| Rapid IO PHY in 65nm | By Quotes | 2.295 μm^2 | 25 MHz | 65 nm | |
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| The IP is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can also be used in any serial interface where timing and electrical specification can be satisfied. This IP has four individual Transmitter (TX) and Receiver (RX) channels, and one common phase lock loop (PLL). | Introduction | |||||
| Oscillator - RC22MHz | By Quotes | None | 22 MHz | 180 nm | |
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| The RC_OSC22M is a low power consumption internal Resistor/Capacitor oscillator with trimming operating frequency. This OSC needs input Bandgap reference voltage to maintain stable operating frequency and decrease power supply effects. The RC-oscillator cell is useful for applications that require an oscillator that utilizes non-external components and has a relaxed frequency tolerance. An enable / disable mode is provided to disable the oscillator. When the oscillator is in the disable mode, the output (CLK22M) goes to a logic level low. It is processed using SMIC’s 0.35μm logic process with an operating supply voltage range of 2.0V ~ 5.5V and a junction temperature range of -40˚ ~ 125˚C. | Introduction | |||||
| 10/100/1000 Ethernet Media Access Controller | By Quotes | None | 125 MHz | 130 nm | |
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| The MAC-1G/MAC is a synthesizable HDL core of a high-speed LAN controller. It implements Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms defined by the IEEE 802.3 standard for media access control over the 10Mbps, 100Mbps and 1Gbps Ethernet. Communication with an external host is implemented via a set of Control and Status Registers and the DMA controller for external shared RAM memory. For data transfers the MAC-1G/MAC operates as a DMA master. It automatically fetches from transmit data buffers and stores receive data buffers into external RAM with minimum CPU intervention. The linked list management enables the use of various memory allocation schemes. There is an interface for external dual port RAMs serving as configurable FIFO memories and there are separate memories for transmit and receive processes. Using the FIFOs additionally isolates the MAC-1G/MAC from an external host and provides resolution in case of latency of an external bus. Application Network Interface Cards (NICs) Routers, switching hubs | Introduction | |||||
| JPEG Decoder | By Quotes | None | 250 MHz | 130 nm | |
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| This JPEG Decoder IP core has been developed to be a complete standards compliant JPEG / MJPEG Hardware Decompressor / Decoder. When decoding JPEG images, pixel throughput can not be fixed for compressed JPEGs of arbitrary quality, as it depends on the compression ratio (bits needed to encode one pixel). To circumvent this limitation JPEG Decoder IP features a dual pixel component pipeline, allowing for greater decoding speeds. | Introduction | |||||
| JPEG Encoder | By Quotes | None | 250 MHz | 130 nm | |
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| This IP core has been developed to be a complete standards compliant JPEG / MJPEG Hardware Compressor / Encoder. The data interfaces in the JPEG Encoder IP Core (JPEGE) use the AXI industry standard. The Master I/O data interfaces use an AXI3 bus, forward compatible with AXI4 interconnects. In order to let you assess the properties of the on-the-fly selectable quality setting, please use the slider below the image in order to see the final compressed image and compression ratio. The JPEG Encoder IP Core has a real throughput of two compressed pixels every three clock cycles at any compression ratio for a chroma subsampling of 4:2:0. To calculate the throughput for your platform. | Introduction | |||||
| H.264 Encoder IP Core | By Quotes | None | 150 MHz | None | |
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| This H.264 Encoder IP core has been developed to be the highest throughput standards compliant hardware H.264 video compressor. The IP offers two encoder variants to meet the different targets of features. The IP include 2 mode. H264E-I: H.264 encoder compliant with CAVLC 4:4:4 Intra Profile (all frames are keyframes) The IP core is smaller but yields less compression. It does not require external memory. H264E-P: H.264 encoder compliant with High 4:4:4 Predictive Profile: The IP core is larger but offers a significantly better compression. Both share the same outstanding processing speed of more than 5.2 pixels encoded per cycle. The data interfaces in the H.264 Encoder IP Core use the AXI industry standard. The Master I/O data interfaces use an AXI3 bus, forward compatible with AXI4 interconnects. | Introduction | |||||
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