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WiFi Frequency Synthesizer IP In 2.4GHz Band 100000 Points 200.000 K μm^2 3.2 GHz 55 nm  
The frequency  synthesizer  uses  a  single  1.25V  power supply.  Good  noise  immunity  allows  this  IP  to  be integrated  in  a  noisy  SOC environment.  The  synthesizer  operates  at  1.5X  WiFi  2.4GHz  band  for  wireless application.  Introduction
Sigma-Delta Stereo CODEC in 55nm By Quotes 562.800 K μm^2 96 KHz 55 nm  
The IP is a high resolution, single-chip stereo CODEC that employs the Sigma-Delta noise shaping technique for 55nm logic process. The ADC, DAC and power amplifier are integrated in it. With 18bit resolution for DAC and 18bit resolution for ADC, The IP is suitable for applications in consumer digital audio systems, automobile audio, multimedia and digital systems. Introduction
Rapid IO PHY in 65nm By Quotes 2.295 μm^2 25 MHz 65 nm  
The IP is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can also be used in any serial interface where timing and electrical specification can be satisfied. This IP has four individual Transmitter (TX) and Receiver (RX) channels, and one common phase lock loop (PLL). Introduction
Dual-Channel 12-bit 80 MSPS ADC IP in UMC 65 nm By Quotes 450.000 μm^2 0.8 MHz 65 nm  
ADC X is an ultra-compact and very low power analog-to-digital converter (ADC) IP. The 12-bit 80 MSPS Dual ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. IP architecture is robust and can be ported to other 65 nm processes.The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. Introduction
10-bit 300 MSPS Video DAC IP in 90 nm 60000 Points 76.000 K μm^2 300 MHz 90 nm  
The  UIP_DAC10-300M_205370  is  a  10-bit  DAC designed  in  low  power  TSMC  90  nm  logic process. It consists of a current steering DAC. The DAC uses a fully differential architecture. The  input  data  of  the  DAC  is  in  1.2V,  in unsigned format.   A 3.3V  supply  is used for  the analog  portion of  the  IP.  This  high  performance  DAC  is designed  for  CVBS  standard  or  RGB  Video signal  bandwidth.  The  IP  consumes  only  41 mA  at  300  MSPS  operation  and  utilizes  a silicon area of only 0.076 mm2. The IP does not  require  any  external  decoupling  and  is ideal for integration in mixed-signal systems.   The  DAC  output  current  is  6-bit programmable.  The  IP  architecture  is  robust and can be ported to other 90 nm processes.   APPLICATIONS Composite Video (CVBS) HDTV RGB Video ​ DAC Output Model Introduction
Triple 10-bit 330 MSPS Video DAC IP in TSMC 90 nm By Quotes 330.000 μm^2 330 MHz 90 nm  
MIC_DAC10X3 is a 10-bit Triple DAC designed in TSMC 90 nm logic process. It consists of a current steering DAC. The DAC uses a fully differential architecture. The input data of the DAC is in 1.2 V, in unsigned format. Introduction
Power Controller By Quotes 0.165 μm^2 None 90 nm  
It is a configurable core that is configured for each specific SoC, delivering all the necessary auxiliary supply, monitoring and protection.  Introduction
[110nm] 10-bit 165 MSPS ADC IP 70000 Points 210.000 K μm^2 165 MHz 110 nm  
UIP_ADC10_165M_213779 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs.   The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances.   The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 48mW at 165 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format.   UIP_ADC10_165M_213779 can be used in the following applications:   ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel ‧IOT Introduction
[110nm]10-bit 80 MSPS ADC IP 60000 Points 210.000 K μm^2 80 MHz 110 nm  
UIP_ADC10_80M_183288 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 80 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs.   The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances.   The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 24mW at 80 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format.   UIP_ADC10_80M_183288 can be used in the following applications:   ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel Introduction
14-Bit 3 MSPS ADC in GSMC110nm 60000 Points 32.000 K μm^2 3 MHz 110 nm  
UIP_ADC14_3M_245303  is  compact  and  low power 14-bit analog-to-digital converter silicon IP.  It  has  20  single-end  input  channel selection  multiplexer  or  10  differential  input channels  selection.  This  ADC  uses  fully differential SAR architecture optimized for low power and small area. The ADC is designed for  high  dynamic  performance  for  input frequencies  up  to  Nyquist  rate.  This  ADC consumes  150  uA  at  3  MSPS  operation  and occupies  silicon  area  of  0.32 mm2 .  The  ADC has  high  immunity  to  substrate  noise  and  is ideal  for  SoC  integration.   APPLICATIONS  General purpose data acquisition Battery monitory system  Temperature monitory system Introduction
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