12-Bit 320MPS IQ DAC in TSMC40LP |
70000 Points |
250.000 K μm^2 |
320 MHz |
180 nm |
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UIP_DAC12X2_320M_922687 is compact and low power 12-bit digital-to-analog converter silicon IP in IBM 180nm SOI process. It features two channel current steering DAC.
This IQ DAC IP is optimized for low power and small area. At 320 MHz conversation rate, it only consumes 63mW and occupies silicon area of 0.25 mm2.
APPLICATIONS
WiFi / LTE / WiMax
Wireless MIMO
Digital Video
Communication Transmit
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Introduction |
12-Bit 800KSPS Low Power SAR-ADC |
By Quotes |
None |
25 MHz |
180 nm |
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The SAR-ADC is a low power ADC that is implemented in Successive Approximation architecture. It can provide 12-bit resolution capability with only 3V supply voltage. It accepts an analog input range from 0 to VCC and digitizes the input at a maximum sampling frequency rate of 800KHz at 5V supply voltage. This ADC also includes MUX design to select 0 of 7 analog inputs. The power dissipation is less than 5mW with 5V power supply. This SAR-ADC is implemented in SMIC 0.18μm generic CMOS technology.
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Introduction |
32 bits RISC Microcontroller |
By Quotes |
33.000 K Gates |
100 MHz |
180 nm |
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The CPU Core is a 32-bit microprocessor. It has a 32-bit data path, a 32-bit register bank, and 32-bit memory interfaces. The processor has a Harvard architecture, which means that it has a separate instruction bus and data bus. This allows instructions and data accesses to take place at the same time, and as a result of this, the performance of the processor increases because data accesses do not affect the instruction pipeline.However, the instruction and data buses share the same memory space (a unified memory system). In other words, you cannot get 8 GB of memory space just because you have separate bus interfaces.
Applications
Wearables
IoT
Motor Control
Appliances
Connectivity
Smart home/building/enterprice/planet
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Introduction |
Oscillator - RC22MHz |
By Quotes |
None |
22 MHz |
180 nm |
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The RC_OSC22M is a low power consumption internal Resistor/Capacitor oscillator with trimming operating frequency. This OSC needs input Bandgap reference voltage to maintain stable operating frequency and decrease power supply effects. The RC-oscillator cell is useful for applications that require an oscillator that utilizes non-external components and has a relaxed frequency tolerance. An enable / disable mode is provided to disable the oscillator. When the oscillator is in the disable mode, the output (CLK22M) goes to a logic level low. It is processed using SMIC’s 0.35μm logic process with an operating supply voltage range of 2.0V ~ 5.5V and a junction temperature range of -40˚ ~ 125˚C.
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Introduction |
300 mA Capless LDO in 180 nm (VLDS0300RNM180) |
By Quotes |
None |
None |
180 nm |
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Noise Quencher® Capless LDO (Silicon-proven 180 nm, 300 mA, excellent supply noise rejection and fast settling)
Noise Quencher® LDOs: This series of low-power, fully-integrated low dropout (LDO) voltage regulators uses our patented Noise Quencher® Technology to provide best-in-class dynamic performance and noise rejection. The IP cores are unconditionally stable across a wide range of load currents and load capacitances and also do not require external components, thus saving package pins and valuable PC board space. These LDOs are optimized for stand-alone power management integrated circuit (PMIC) ASSPs and other analog and digital applications.
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Introduction |
12-Bit 50 MSPS ADC in IBM 180 SOI |
By Quotes |
280.000 μm^2 |
50 MHz |
180 nm |
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MICIP_ADC12 is compact and low power 12-bit analog-to-digital converter silicon IP. This ADC uses 1.5b/stage pipelined architecture optimized for low power and small area.
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Introduction |
12-Bit 320MSPS IQ DAC in IBM SOI 180nm |
By Quotes |
254.000 K μm^2 |
320 MHz |
180 nm |
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MIC_DAC12X2 is compact and low power 12-bit digital-to-analog converter
silicon IP in IBM 180nm SOI process. It features two channel current steering DAC.
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Introduction |
10-Bit 1MSPS Cyclic A/D Converter |
By Quotes |
300.000 K μm^2 |
10.12 MHz |
250 nm |
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This IP is a 1MSPS , single supply , 10-bit analog-to-digital converter (ADC) that combines a low cost, high speed CMOS process and a novel architecture. It is a complete ADC with an on chip, high performance sample-and-hold amplifier and voltage reference. An external reference can be chosen to suit the dc accuracy and temperature drift requirements of the application. The device uses a cyclic architecture with digital error correction logic to guarantee no missing code over the full operating range.
The input of this ADC is highly flexible. A truly differential input structure allows for both single-ended and differential input interface of varying span. The sample-and-hold amplifier (SHA) is equally suited for multiplexed systems that switched full-scale voltage levels in successive channels as well as sampling single-channel inputs at frequencies up to and beyond the Nyquist rate of 500KHz.
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Introduction |