ITU-R BT.656 video decoder |
By Quotes |
None |
300 MHz |
None |
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DEC_BT656 is a digital video decoder with integrated colour-space converter. It's function is to extract the valid pixels from a BT.656 video stream and convert them to 24-bit RGB for subsequent processing.
Pixels are extracted from the BT.656 input stream and converted to RGB888 format.
Application
BT.656 input video capture and processing
PAL & NTSC SDTV interlaced format conversion
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Introduction |
Color-space Converter |
By Quotes |
None |
400 MHz |
None |
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This IP is a fully pipelined color-space converter that converts pixels between the RGB and YCbCr color spaces. In total, the IP Core package contains two distinct modules – one module that converts from 24-bit RGB to 30-bit 4:4:4 YCbCr and the other that performs the reciprocal operation from 4:4:4 YCbCr to RGB.
Application
Digital video and image processing
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Introduction |
IIR filter Second-Order |
By Quotes |
None |
150 MHz |
None |
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This IP is a second order IIR filter sometimes referred to as a 'bi-quad'. Internally, it has a fully pipelined architecture permitting the highest possible sample rates for IIR filtering.
Values are sampled on the rising clock-edge of clk when EN is high. The latency of the IIR filter between the first input sample and the first output sample is 7 clock cycles.
Applicaion
IIR filtering in higher sample-rate applications
General purpose high-pass, band-pass and low-pass filters
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Introduction |
High-speed FIR Filter with symmetry |
By Quotes |
None |
500 MHz |
None |
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This IP is an FIR filter IP Core with symmetrical coefficients and an even or odd number of filter taps. The architecture exploits the symmetry of the coefficients using half the number of multipliers compared to a normal FIR implementation. The result is a filter with a reduced area footprint while still maintaining the capacity for high sample rates.
Application
High-speed filter applications where resources are limited
General purpose FIR filters with symmetrical coefficients
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Introduction |
Binary FSK Demodulator |
By Quotes |
None |
200 MHz |
None |
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This IP is a precision Binary-FSK Demodulator IP Core based on a non-coherent receiver design. The demodulator is fully programmable, allowing for a varied range of symbol rates and mark/space tone frequencies. Input data samples may be either complex or real for support of either passband or baseband signals. The module allows easy connectivity to an external ADC with up to 16-bit signed input samples.
Applications:
Short range telemetry
Software radio
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Introduction |
Video and Audio develop platform |
By Quotes |
None |
None |
None |
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Single Chip Solution
32-bit RISC MCU
SPI/UART/I2C/GPIO
Video Process Engine
Video DAC/Audio DAC
USB 2.0
Video Scaler
DDR4
Easy Integrated Customer’s Logic
Application
DVR and POS DVR
ATM machine surveillance
Home stay monitoring
Multiple channel IP camera
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Introduction |
H.264 Encoder IP Core |
By Quotes |
None |
150 MHz |
None |
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This H.264 Encoder IP core has been developed to be the highest throughput standards compliant hardware H.264 video compressor.
The IP offers two encoder variants to meet the different targets of features.
The IP include 2 mode.
H264E-I: H.264 encoder compliant with CAVLC 4:4:4 Intra Profile (all frames are keyframes)
The IP core is smaller but yields less compression. It does not require external memory.
H264E-P: H.264 encoder compliant with High 4:4:4 Predictive Profile:
The IP core is larger but offers a significantly better compression.
Both share the same outstanding processing speed of more than 5.2 pixels encoded per cycle.
The data interfaces in the H.264 Encoder IP Core use the AXI industry standard.
The Master I/O data interfaces use an AXI3 bus, forward compatible with AXI4 interconnects.
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Introduction |
Binary PSK Demodulator |
By Quotes |
None |
200 MHz |
None |
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IP is a Binary-PSK demodulator based on a multiply-filter-divide architecture. The design is robust and flexible and allows easy connectivity to an external ADC.
As the the carrier recovery circuit is open-loop, there is no feedback path or loop-filter to configure. This results in an extremely simple circuit with a very fast carrier acquisition time. The only requirement is that the user set the desired symbol period and a suitable threshold level for the bit decisions at the symbol decoder. The other design parameters including carrier frequency, symbol rate and sampling frequency should be specified by the user before delivery of the IP Core 1 .
The input data samples are 16-bit signed (2's complement) values that are synchronous with the system clock. Input values are sampled on the rising edge of clk when en is high.
Application
Robust, low bandwidth RF applications for small FPGA devices
SRD and ISM band devices
Medium to long-range telemetry
Software radio
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Introduction |
Digital Down Converter with configurable Decimation Filter |
By Quotes |
None |
250 MHz |
None |
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DDC is a complex-valued digital down-converter with a configurable number of decimation stages. The design is ideal for high sample-rate applications and permits a digital input signal to be mixed-
down and re-sampled at a lower data rate. The DDC is suitable for the down-conversion of any digitally modulated signal to baseband – an essential step before digital processing.
The DDC features a high-precision 16-bit DDS oscillator for the digital mixing stage. This oscillator is fully programmable and offers excellent phase and frequency resolution. The digital mixing stage is a complex multiplier that allows the mixing of both real and imaginary (I/Q) inputs. If only real inputs are required, then the imaginary input (q_in) should be tied low.
The output decimation stage features a configurable decimate-by-2N poly-phase filter for both I and Q channels. Each filter stage is highly optimized to use only 12 multipliers while still achieving 80 dB of stop-band attenuation.
Application
Compatible with any digital modulation scheme - e.g. QPSK, BPSK, QAM, WiMAX, WCDMA, COFDM etc.
Conversion of IF signals to baseband frequencies for subsequent processing
Digital I/Q Demodulators
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Introduction |
FIR filter |
By Quotes |
None |
300 MHz |
None |
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FIR_F is an FIR filter implementation designed for very high sample rate applications. Organized as a systolic array the filter is modular and fully scalable, permitting the user to specify large order filters without compromising maximum attainable clock-speed. Mathematically, the filter implements the difference equation:
y[n] = h0 x[n] + h1 x[n−1] + ... + hN x[n−N ]
In the above equation, the input signal is x[n], the output signal is y[n] and h0 to hN represent the filter coefficients. The number N is the filter order, the number of filter taps being equal to N+1.
Application
General purpose FIR filters with odd or even numbers of taps
Filters with arbitrary sets of coefficients
Very high-speed filtering applications
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Introduction |