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| PLL 1600M UMC 28 nm logic and Mixed-Mode HPC process | By Quotes | 270.000 μm^2 | 1.6 GHz | 28 nm |  |
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| A Phase-Locked Loop (PLL) with an operating frequency ranging from 200 MHz to 1600 MHz. This PLL is designed with the UMC 28 nm logic and Mixed-Mode HPC process. It can be integrated into a chip to generate a high-speed clock. The embedded divide-by-4 loop divider allows users to boost the output frequency of up to 1600 MHz. | Introduction | |||||
| PLL 800M UMC 28 nm logic and Mixed-Mode HPC process | By Quotes | 230.000 μm^2 | 800 MHz | 28 nm | |
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| It is a 28-nm low-power spread spectrum clock generator that supports an operating frequency ranging from 400 MHz to 800 MHz and from 200 MHz to 400 MHz. This SSCG is programmable to perform the frequency synthesis and spread-spectrum function for the Electro Magnetic Interference (EMI) reduction in various ASIC designs. | Introduction | |||||
| PLL 1300M UMC 28 nm logic and Mixed-Mode HPC process | By Quotes | 109.850 K μm^2 | 50 MHz | 28 nm | |
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| It is used to generate a stable, high-speed clock from an external slower clock signal. It integrates one Voltage-Controlled Oscillator (VCO), one Phase-Frequency Detector (PFD), one Low-Pass Filter (LPF), one 8-bit programmable divider, and other associated support circuitries. This PLL supports an operating voltage ranging from 0.81 V to 0.99 V with an operating junction temperature ranging between -40 °C and 125 °C. This IP uses the input operating frequency of PFD ranging from 6 MHz to 25 MHz and generates the output frequency ranging from 25 MHz to 1300 MHz. The jitter performance of a PLL is highly dependent on the floor plan of ASIC. Because PLL is a sensitive cell when integrated into an ASIC design, the best way to maximize its capacity is to keep PLL away from the noisy blocks in the core region, such as the memory block and the high-driving logic circuit, and the I/O region, such as the high-driving I/O. This PLL must be placed around the I/O area. Providing sufficient space between this PLL and the noisy blocks is a simple and effective approach to reduce the coupled substrate noise. | Introduction | |||||
| USB 3.2 G EN 1 OTG T RANSCEIVER | By Quotes | None | 12 MHz | 28 nm | |
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| MIP300HJ0C │ MIP300NSHJ0C_SB are USB transceivers that provide a complete range of the host and peripheral functions. They are fully compliant with the USB 3.1 Gen1 and USB 2.0 OTG specifications. In the SuperSpeed mode, this transceiver is capable of transmitting or receiving data at 5.0 Gbps. When operating in the High-Speed mode, this transceiver is capable of transmitting or receiving data at 480 Mbps. | Introduction | |||||
| DSP-BASED ETHERNET TRANSCEIVER in UMC 28nm HPC+ | By Quotes | None | 25 MHz | 28 nm | |
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| A 28nm DPS-based Gigabit Ethernet transceiver. Highly intergrated 1000BASE-T, 100BASE-TX, 100BASE-FX and 10BASE-Te. Fully compliant with 100BASE-FX IEEE 802.2u standard | Introduction | |||||
| Triple 10-bit 330 MSPS Video DAC IP in TSMC 90 nm | By Quotes | 330.000 μm^2 | 330 MHz | 90 nm | |
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| MIC_DAC10X3 is a 10-bit Triple DAC designed in TSMC 90 nm logic process. It consists of a current steering DAC. The DAC uses a fully differential architecture. The input data of the DAC is in 1.2 V, in unsigned format. | Introduction | |||||
| PCI Express Gen4 PHY IP in 28nm HPC+ | By Quotes | None | 25 MHz | 28 nm | |
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| The Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE v4.4 inter- face spec. Lower power consumption is achieved due to support of addition- al PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption. | Introduction | |||||
| PCI Express Gen4 PHY IP in TSMC 12nm FFC | By Quotes | None | 25 MHz | 12 nm | |
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| The Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 4.0 Base Specification with support of PIPE v4.4 inter- face spec. Lower power consumption is achieved due to support of addition- al PLL control, reference clock control, and embedded power gating control. Also, since aforementioned low power mode setting is configurable, the PHY is widely applicable for various scenarios under different consideration of power consumption. | Introduction | |||||
| MIPI M-PHY Gear 4 IP in TSMC 28nm HPC+ | By Quotes | None | 11 GHz | 28 nm | |
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| MIPI M-PHY Gear 4 IP is compliant with the latest MIPI. Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification. A serial interface technology with high bandwidth capabilities and supports HS Gear4 rates up to 11.6Gbps, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. The MIPI M-PHY Gear 4 IP compliant to the RMMI interface which allows UniPro controller and UFS Controller. | Introduction | |||||
| MIPI M-PHY Gear 4 IP in TSMC 12nm FFC | By Quotes | None | 11 GHz | 12 nm | |
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| MIPI M-PHY Gear 4 IP is compliant with the latest MIPI. Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification. A serial interface technology with high bandwidth capabilities and supports HS Gear4 rates up to 11.6Gbps, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. The MIPI M-PHY Gear 4 IP compliant to the RMMI interface which allows UniPro controller and UFS Controller. | Introduction | |||||
| μIP | Price | Logic Gate Count | Clock Rate | Technology | Ratings | |
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