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| Clock divider by 3 | 100 Points | 52.000 Gates | 370 MHz | 130 nm |  |
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| There are 2 types of circuits in digital logic world. One is combinational, and the other is sequential. The difference between them is that the latter one has storage (memory) while the former one does not. Thus, in contrast to combinational circuits, whose output depends only on the current values of its inputs, the output of sequential circuits depends not only on the current values of its inputs but also on the past values of them. Based on the characteristic of sequential circuits, we can build counters. In addition, we can further build clock dividers with the counters we designed | Introduction | |||||
| Triple 10-bit 330 MSPS Video DAC IP in TSMC 90 nm | By Quotes | 330.000 μm^2 | 330 MHz | 90 nm | |
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| MIC_DAC10X3 is a 10-bit Triple DAC designed in TSMC 90 nm logic process. It consists of a current steering DAC. The DAC uses a fully differential architecture. The input data of the DAC is in 1.2 V, in unsigned format. | Introduction | |||||
| 12-Bit 320MPS IQ DAC in TSMC40LP | 70000 Points | 250.000 K μm^2 | 320 MHz | 180 nm | |
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| UIP_DAC12X2_320M_922687 is compact and low power 12-bit digital-to-analog converter silicon IP in IBM 180nm SOI process. It features two channel current steering DAC. This IQ DAC IP is optimized for low power and small area. At 320 MHz conversation rate, it only consumes 63mW and occupies silicon area of 0.25 mm2. APPLICATIONS WiFi / LTE / WiMax Wireless MIMO Digital Video Communication Transmit | Introduction | |||||
| 12-Bit 320MSPS IQ DAC in IBM SOI 180nm | By Quotes | 254.000 K μm^2 | 320 MHz | 180 nm | |
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| MIC_DAC12X2 is compact and low power 12-bit digital-to-analog converter silicon IP in IBM 180nm SOI process. It features two channel current steering DAC. | Introduction | |||||
| 10-bit 300 MSPS Video DAC IP in 90 nm | 60000 Points | 76.000 K μm^2 | 300 MHz | 90 nm | |
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| The UIP_DAC10-300M_205370 is a 10-bit DAC designed in low power TSMC 90 nm logic process. It consists of a current steering DAC. The DAC uses a fully differential architecture. The input data of the DAC is in 1.2V, in unsigned format. A 3.3V supply is used for the analog portion of the IP. This high performance DAC is designed for CVBS standard or RGB Video signal bandwidth. The IP consumes only 41 mA at 300 MSPS operation and utilizes a silicon area of only 0.076 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The DAC output current is 6-bit programmable. The IP architecture is robust and can be ported to other 90 nm processes. APPLICATIONS Composite Video (CVBS) HDTV RGB Video DAC Output Model | Introduction | |||||
| UART Serial Interface Controller | By Quotes | None | 300 MHz | None | |
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| UART compatible Serial Interface Controller with receive and transmit FIFOs and support for all standard bit rates from 9600 to 921600 baud. Applications UART Communications RS232, RS422, RS485 etc. Micro-controller interfacing | Introduction | |||||
| I2C Master Serial Interface Controller | By Quotes | None | 300 MHz | None | |
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| Master serial controller compatible with the popular Philips® I2C standard. Features a simple command interface and permits multiple I2C slaves to be controlled directly from ASIC device. Supports standard (100 kbits/s), fast (400 kbits/s) and custom data rates well above 4 Mbits/s. Setup and hold-times on the SDA pin are fully configurable. Applications Inter-chip board-level communications Standard 2-wire comms between a wide range of peripherals, MCUs and COTs ICs | Introduction | |||||
| I2C Slave Serial Interface Controller | By Quotes | None | 300 MHz | None | |
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| Slave serial controller compatible with the popular Philips® I2C standard. Permits an I2C Master to communicate with your ASIC device via a set of user-defined config and status registers. Supports standard (100 kbits/s), fast (400 kbits/s) and custom rates in excess of 4 Mbits/s. Applications I2C slave communication via your ASIC Inter-chip board-level communications | Introduction | |||||
| Video Frame Buffer | By Quotes | None | 300 MHz | None | |
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| VID_FB is a high-speed multi-format video frame buffer that asynchronously samples an input video stream and buffers it in an external memory. Output pixels are read out of the buffer and synchronised to the system clock domain. The VID_FB will automatically adapt to different input and output frame rates. If the input frame rate is too high, then the VID_FB will cleanly drop or 'skip' an input frame. Likewise, if the output frame rate is higher than the input frame rate, then frames will be repeated 3 . The result is a system that seamlessly adapts to the different frame rates at the input and output of the VID_FB. Applications Buffering video frames in external memory Real-time digital video applications Genlocking of multiple video sources | Introduction | |||||
| ITU-R BT.656 video decoder | By Quotes | None | 300 MHz | None | |
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| DEC_BT656 is a digital video decoder with integrated colour-space converter. It's function is to extract the valid pixels from a BT.656 video stream and convert them to 24-bit RGB for subsequent processing. Pixels are extracted from the BT.656 input stream and converted to RGB888 format. Application BT.656 input video capture and processing PAL & NTSC SDTV interlaced format conversion | Introduction | |||||
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