Needhelp
?
| Periodic waveform generator | By Quotes | None | 200 MHz | None |  |
|
| The IP Core is a high-precision Direct Digital Synthesizer 2 used for the generation of periodic waveforms. On each rising-edge of the sample clock, the phase in the phase accumulator is incremented by the value phase_inc. This phase is quantized to 16-bits and passed as an address to a look-up table which converts the phase into a waveform. In addition to the quadrature outputs sin_out and cos_out, the IP also provides square wave and sawtooth outputs: squ_out and saw_out. All output values are 16-bit signed numbers. Appliaction Digital up/down converters and mixers Versatile waveform generation Digital oscillators Digital modulation | Introduction | |||||
| Motion-adaptive Video Deinterlacer | By Quotes | None | 200 MHz | None | |
|
| The IP Core is a studio quality 24-bit RGB video deinterlacer capable of generating progressive output video at any resolution up to 216 x 216 pixels. The design is fully programmable and supports any desired interlaced video format. The design allows for three possible deinterlacing schemes. These are: weave, bilinear interpolation or motion-adaptive interpolation. The weave approach applies no filtering and may be useful to obtain a 'raw' interlaced format for subsequent processing. The other two methods are classed as 'inter-field' interpolation methods as spatial filtering is performed between both odd and even fields to achieve a clean and progressive output. The relative merits and disadvantages of each scheme are discussed further into the document. The deinterlacer core features a fully integrated video frame buffer. This buffer is completely 'elastic' and will dynamically skip and/or repeat frames depending on the input and output frame rates. All frame buffer management is handled internally with the provision of a simple memory interface for storing odd and even fields off-chip. The memory interface is 128-bits wide and is completely generic. All memory transfers are sequential bursts of N x 128-bit words and may be adapted for connection to a variety of memory types such as SDRAM, DDR2 or DDR3. Application Digital TV set-top boxes. Industrial imaging. Automotive, home and personal media solutions Conversion of 'legacy' SDTV formats to HDTV video formats Generating progressive RGB video via inexpensive PAL/NTSC decoder chips Studio-quality video de-interlacing | Introduction | |||||
| Multi-format Video Deinterlacer | By Quotes | None | 200 MHz | None | |
|
| The IP Core is a high quality 24-bit RGB video deinterlacer capable of generating progressive output video at up to 4096x4096 pixels in resolution. The design is fully customizable, supporting any desired interlaced video format. The deinterlacer allows for three possible filter algorithms - either BOB, ELA or LCI. All three methods are 'intra-field' methods that perform spatial filtering within the same field. For this reason, the output video is not subject to combing or tearing which is characteristic of a traditional 'weave' approach. Each algorithm has it relative merits in terms of image quality and hardware complexity. In particular, the enhanced LCI algorithm provides excellent all-round performance with reduced image softening and crisp clean edges. Application Conversion of 'legacy' SDTV formats to HDTV video formats Generating progressive RGB video via inexpensive PAL/NTSC decoder chips High-quality video de-interlacing without the overhead of a frame buffer Digital TV set-top boxes and home media solutions | Introduction | |||||
| Cold Wallet Total solution | By Quotes | None | 200 MHz | None | |
|
| This Cold Wallet Total solution can decrease timing for developing. Single chip solution. Include software solution for Bitcoin transaction. Secure Element 32 bit MCU Crypto Engine Hardware DSE USB2.0 device CRC calculation unit Application : Cold Wallet | Introduction | |||||
| USB 2.0 ON-THE-GO CONTROLLER | By Quotes | 75.000 K Gates | 200 MHz | None | |
|
| This is a universal serial bus (USB) 2.0 On-The-Go (OTG) Controller, which can play dual-role, as a host or a device controller. When it acts as a host, it contains a USB host controller to support all speed transactions. | Introduction | |||||
| SPI slave in mode 2 | 1000 Points | 254.000 Gates | 192 MHz | 130 nm | |
|
| The Serial Peripheral Interface (SPI) bus, established by Motorola, is a synchronous serial data link. It operates in master/slave and full duplex styles. That is, when a master device initiates a transaction and communicates with a certain slave device, they exchange data bit-by-bit. Furthermore, the single master communication is applied to the SPI bus. Thus, there is always a single master device (with one or more slave devices) on it. The SPI bus contains 4 wires, with each named SCK, MOSI, MISO and SS_n respectively. You may also find alternative naming conventions elsewhere. The following table lists their functions and directions: The typical SPI bus architecture is designed as follows: When the SPI master device wants to communicate with a certain slave device, it asserts the SS_n line of that slave device, and then exchange data using the MOSI and MISO lines based on the toggling SCK line. With clock polarity (CPOL) and clock phase (CPHA) set to different values, the SPI bus can operate in 4 modes. These modes are listed in the following table, where provide means that the communicating master and slave devices provide data on the MOSI and MISO lines respectively on the other hand, capture means that the communicating master and slave devices capture data on the MISO and MOSI lines respectively: | Introduction | |||||
| 10-bit 165 MSPS ADC IP in 28 nm | 80000 Points | 70.000 K μm^2 | 165 MHz | 28 nm | |
|
| UIP_ADC10_165M_564144 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances. The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 12mW at 165 MSPS operation and requires silicon area of 0.07 mm^2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format. UIP_ADC10_165M_564144 can be used in the following applications: ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel | Introduction | |||||
| 10-bit 165 MSPS ADC IP in 28 nm | 80000 Points | 70.000 K μm^2 | 165 MHz | 28 nm | |
|
| UIP_ADC10_165M_809744 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances. The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 12mW at 165 MSPS operation and requires silicon area of 0.07 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format. UIP_ADC10_165M_809744 can be used in the following applications: ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel ‧IOT | Introduction | |||||
| 10-bit 165 MSPS ADC IP in 130 nm | 70000 Points | 210.000 K μm^2 | 165 MHz | 130 nm | |
|
| UIP_ADC10_165M_166413 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances. The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 48mW at 165 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format. UIP_ADC10_165M_166413 can be used in the following applications: ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel ‧IOT | Introduction | |||||
| [110nm] 10-bit 165 MSPS ADC IP | 70000 Points | 210.000 K μm^2 | 165 MHz | 110 nm | |
|
| UIP_ADC10_165M_213779 is an ultra-compact and very low power analog-to-digital converter (ADC) silicon IP. The 10-bit 165 MSPS ADC includes an internal custom bandgap voltage reference. It is capable of supplying bias currents to other parallel ADCs. The ADC uses fully differential pipeline architecture with custom low-disturbance digital correction technique which allows single supply bus for both digital and analog. The ADC is designed for high dynamic performance for input frequencies up to Nyquist. This makes the IP perfectly suitable for video, imaging and communication appliances. The IP is available in different metal options as well as deep N-well (DNW) option for SoC with high level of substrate noise. It consumes only 48mW at 165 MSPS operation and requires silicon area of 0.21 mm2. The IP does not require any external decoupling and is ideal for integration in mixed-signal systems. The output data of ADC is available in 2’s complement format. UIP_ADC10_165M_213779 can be used in the following applications: ‧Digital imaging ‧TV/Video ‧Wireless LAN ‧Rx communication channel ‧IOT | Introduction | |||||
| μIP | Price | Logic Gate Count | Clock Rate | Technology | Ratings | |
|---|---|---|---|---|---|---|