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| Bilinear Video Scaling Engine | By Quotes | None | 250 MHz | None |  |
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| This IP is a very high quality video scaler capable of generating interpolated output images from 16x16 up to 216 x 216 pixels in resolution. The architecture permits seamless scaling (either up or down) depending on the chosen scale factor. Internally, the scaler uses a 24-bit accumulator and a bank of polyphase FIR filters with 16 phases or interpolation points. All filter coefficients are programmable, allowing the user to define a wide range of filter characteristics. Pixels flow in and out of the scaling engine in accordance with the valid-ready pipeline protocol.As such, the pipeline protocol allows both input and output interfaces to be stalled independently. The scaler is partitioned into a horizontal scaling section in series with avertical scaling section. Application Conversion of popular video formats to any other resolution such as VGA to XGA, SVGA to HD1080 etc. Picture in Picture (PiP) applications High quality 24-bit RGB/YCbCr video scaling | Introduction | |||||
| Digital Video overlay module | By Quotes | None | 250 MHz | None | |
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| This IP is a highly versatile video multiplexer that allows one video stream to be inserted over another. By cascading a series of video overlay modules together, any number of video sources may be multiplexed together. The module supports input video streams of any resolution or aspect ratio up to 216 x 216 pixels in size. Video overlay parameters may be changed on a frame-by-frame basis to dynamically change the size and position of the video overlay. Pixels and syncs flow in and out of the video overlay module in accordance with the valid-ready pipeline protocol. The pipeline protocol allows both input and output interfaces to be stalled independently. In addition, the overlay module supports a number of blending operations including an 8-bit alpha channel and bitwise AND, OR and XOR functions. Application Network and Tactical operations centres Digital-video special effects Broadcast TV and film production CCTV and security camera systems | Introduction | |||||
| SPI slave in mode 0 | 1000 Points | 274.000 Gates | 243 MHz | 130 nm | |
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| The Serial Peripheral Interface (SPI) bus, established by Motorola, is a synchronous serial data link. It operates in master/slave and full duplex styles. That is, when a master device initiates a transaction and communicates with a certain slave device, they exchange data bit-by-bit. Furthermore, the single master communication is applied to the SPI bus. Thus, there is always a single master device (with one or more slave devices) on it. The SPI bus contains 4 wires, with each named SCK, MOSI, MISO and SS_n respectively. You may also find alternative naming conventions elsewhere. The following table lists their functions and directions: The typical SPI bus architecture is designed as follows: When the SPI master device wants to communicate with a certain slave device, it asserts the SS_n line of that slave device, and then exchange data using the MOSI and MISO lines based on the toggling SCK line. With clock polarity (CPOL) and clock phase (CPHA) set to different values, the SPI bus can operate in 4 modes. These modes are listed in the following table, where provide means that the communicating master and slave devices provide data on the MOSI and MISO lines respectively on the other hand, capture means that the communicating master and slave devices capture data on the MISO and MOSI lines respectively: | Introduction | |||||
| 8-bit / 16-bit Flash memory controller | By Quotes | None | 200 MHz | None | |
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| FLASH memory controller ideal for interfacing to a wide range of parallel FLASH memory components . Features a fully synchronous command interface and a set of configurable timing parameters for compatibility with different devices. Applications Any application where non-volatile storage is required Offline storage of parameters and data via your Chip | Introduction | |||||
| ITU-R BT.656 video encoder | By Quotes | None | 200 MHz | None | |
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| ITU-R_BT is a digital video encoder with integrated colour-space converter. The encoder accepts 24-bit RGB pixels from sequential odd and even fields. These pixels are then mapped to the YCbCr colour-space and formatted correctly into a BT output stream. The output of the encoder generates an industry standard ITU-R BT.656 format video stream together with a video_val signal that is asserted with the first valid byte of the output stream. Applications BT.656 output video generation PAL & NTSC SDTV video format conversion | Introduction | |||||
| Binary FSK Demodulator | By Quotes | None | 200 MHz | None | |
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| This IP is a precision Binary-FSK Demodulator IP Core based on a non-coherent receiver design. The demodulator is fully programmable, allowing for a varied range of symbol rates and mark/space tone frequencies. Input data samples may be either complex or real for support of either passband or baseband signals. The module allows easy connectivity to an external ADC with up to 16-bit signed input samples. Applications: Short range telemetry Software radio | Introduction | |||||
| Binary PSK Demodulator | By Quotes | None | 200 MHz | None | |
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| IP is a Binary-PSK demodulator based on a multiply-filter-divide architecture. The design is robust and flexible and allows easy connectivity to an external ADC. As the the carrier recovery circuit is open-loop, there is no feedback path or loop-filter to configure. This results in an extremely simple circuit with a very fast carrier acquisition time. The only requirement is that the user set the desired symbol period and a suitable threshold level for the bit decisions at the symbol decoder. The other design parameters including carrier frequency, symbol rate and sampling frequency should be specified by the user before delivery of the IP Core 1 . The input data samples are 16-bit signed (2's complement) values that are synchronous with the system clock. Input values are sampled on the rising edge of clk when en is high. Application Robust, low bandwidth RF applications for small FPGA devices SRD and ISM band devices Medium to long-range telemetry Software radio | Introduction | |||||
| Text Overlay Module | By Quotes | None | 200 MHz | None | |
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| The IP Core is a highly versatile On Screen Display (OSD) module that allows text and bitmap graphics to be inserted over RGB video. The module supports a wide range of text effects and the programming interface is very simple. Text is written to a 64x32 character buffer which is mapped (via a bitmap ROM) directly to the display. The characters in the buffer are displayed in a 'TEXT BOX' which may be positioned anywhere in the video display area. Bitmaps for each character are stored in a ROM which may be modified to support different font styles or bitmap graphics. Pixels and syncs flow in and out of the overlay module in accordance with the valid-ready pipeline protocol. Application Window movement in the same manner as a 2D 'BitBlt' Terminal and Console windows Low cost text and graphics applications Digital TV and home-media solutions | Introduction | |||||
| 2D Graphics Overlay | By Quotes | None | 200 MHz | None | |
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| This is a highly versatile on-screen display that allows high-quality anti-aliased bitmap graphics to be inserted over RGB video. The module supports a wide range of graphics effects and the programming interface is very simple to use. The bitmap overlay is partitioned into an array of tiles which are addressed by means of an 8-bit value stored in a 64x64 tile buffer. There are four tile sizes available - either 8x8, 16x16, 32x32 or 64x64. The tiles in the buffer are displayed in a graphics window which may be positioned anywhere within the display area. Bitmaps for each tile are stored in a user-defined ROM which can contain up to 256 different bitmaps stored over three bit-planes. Depending on the chosen graphics mode, the 3-bits per pixel may be used to select one colour from a palette of eight, eight levels of alpha transparency or seven colours on a transparent background. Pixels and syncs flow in and out of the overlay module in accordance with the valid-ready pipeline protocol. Application Animated 2D graphics including hardware sprites, mouse pointers, cursors , parallax scrolling, moving banners etc. Interactive guides, menus, tables, lists etc. Digital TV and home-media solutions Professional and functional 2D graphic displays and video overlays | Introduction | |||||
| Precision Tone Decoder | By Quotes | None | 200 MHz | None | |
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| The IP is a precision tone decoder with the capacity to support either real or complex data samples. Samples are first mixed-down to baseband before subsequent filtering and tone detection. The centre frequency of the tone is fully programmable and is generated by a local oscillator (DDS). The DDS has an SFDR of better than 80 dBs (with phase dithering) and a theoretical SNR of approximately 100 dBs. After down-conversion, 2 paths are filtered to remove components above the tone of interest. The characteristics of these filters may be changed depending on the desired detection bandwidth and response time. Finally, a power function is used to compute the relative magnitude of the signal after filtering. Application Precision frequency monitoring and control FSK / OOK / ASK demodulation Touch tone decoding (e.g. DTMF tones) Complex digital down conversion | Introduction | |||||
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