Needhelp
?
| Video Frame Buffer | By Quotes | None | 300 MHz | None |  |
|
| VID_FB is a high-speed multi-format video frame buffer that asynchronously samples an input video stream and buffers it in an external memory. Output pixels are read out of the buffer and synchronised to the system clock domain. The VID_FB will automatically adapt to different input and output frame rates. If the input frame rate is too high, then the VID_FB will cleanly drop or 'skip' an input frame. Likewise, if the output frame rate is higher than the input frame rate, then frames will be repeated 3 . The result is a system that seamlessly adapts to the different frame rates at the input and output of the VID_FB. Applications Buffering video frames in external memory Real-time digital video applications Genlocking of multiple video sources | Introduction | |||||
| ITU-R BT.656 video decoder | By Quotes | None | 300 MHz | None | |
|
| DEC_BT656 is a digital video decoder with integrated colour-space converter. It's function is to extract the valid pixels from a BT.656 video stream and convert them to 24-bit RGB for subsequent processing. Pixels are extracted from the BT.656 input stream and converted to RGB888 format. Application BT.656 input video capture and processing PAL & NTSC SDTV interlaced format conversion | Introduction | |||||
| FIR filter | By Quotes | None | 300 MHz | None | |
|
| FIR_F is an FIR filter implementation designed for very high sample rate applications. Organized as a systolic array the filter is modular and fully scalable, permitting the user to specify large order filters without compromising maximum attainable clock-speed. Mathematically, the filter implements the difference equation: y[n] = h0 x[n] + h1 x[n−1] + ... + hN x[n−N ] In the above equation, the input signal is x[n], the output signal is y[n] and h0 to hN represent the filter coefficients. The number N is the filter order, the number of filter taps being equal to N+1. Application General purpose FIR filters with odd or even numbers of taps Filters with arbitrary sets of coefficients Very high-speed filtering applications | Introduction | |||||
| Half-band Nyquist decimation filter | By Quotes | None | 300 MHz | None | |
|
| This is a polyphase decimation filter that permits the down-sampling of an input signal by any power of 2. The filter core is organized as a highly optimized systolic array, allowing the user to specify very large decimation factors while keeping resource costs to a minimum. Input data is sampled on the rising clock-edge of clk when CLK_EN is active high. Internally, the samples are filtered and decimated then presented at the output interface, Y_OUT.The output signal EN_OUT is the output clock-enable signal that indicates when an output sample is valid. Application Decimation by a wide range of factors from 2 to 2N Reduction of input sample rate to make subsequent signal processing easier Decimation of signals after digital-down-conversion | Introduction | |||||
| 12-Bit 320MPS IQ DAC in TSMC40LP | 70000 Points | 250.000 K μm^2 | 320 MHz | 180 nm | |
|
| UIP_DAC12X2_320M_922687 is compact and low power 12-bit digital-to-analog converter silicon IP in IBM 180nm SOI process. It features two channel current steering DAC. This IQ DAC IP is optimized for low power and small area. At 320 MHz conversation rate, it only consumes 63mW and occupies silicon area of 0.25 mm2. APPLICATIONS WiFi / LTE / WiMax Wireless MIMO Digital Video Communication Transmit | Introduction | |||||
| 12-Bit 320MSPS IQ DAC in IBM SOI 180nm | By Quotes | 254.000 K μm^2 | 320 MHz | 180 nm | |
|
| MIC_DAC12X2 is compact and low power 12-bit digital-to-analog converter silicon IP in IBM 180nm SOI process. It features two channel current steering DAC. | Introduction | |||||
| Triple 10-bit 330 MSPS Video DAC IP in TSMC 90 nm | By Quotes | 330.000 μm^2 | 330 MHz | 90 nm | |
|
| MIC_DAC10X3 is a 10-bit Triple DAC designed in TSMC 90 nm logic process. It consists of a current steering DAC. The DAC uses a fully differential architecture. The input data of the DAC is in 1.2 V, in unsigned format. | Introduction | |||||
| Clock divider by 3 | 100 Points | 52.000 Gates | 370 MHz | 130 nm | |
|
| There are 2 types of circuits in digital logic world. One is combinational, and the other is sequential. The difference between them is that the latter one has storage (memory) while the former one does not. Thus, in contrast to combinational circuits, whose output depends only on the current values of its inputs, the output of sequential circuits depends not only on the current values of its inputs but also on the past values of them. Based on the characteristic of sequential circuits, we can build counters. In addition, we can further build clock dividers with the counters we designed | Introduction | |||||
| Color-space Converter | By Quotes | None | 400 MHz | None | |
|
| This IP is a fully pipelined color-space converter that converts pixels between the RGB and YCbCr color spaces. In total, the IP Core package contains two distinct modules – one module that converts from 24-bit RGB to 30-bit 4:4:4 YCbCr and the other that performs the reciprocal operation from 4:4:4 YCbCr to RGB. Application Digital video and image processing | Introduction | |||||
| Video Timing Generator | By Quotes | None | 400 MHz | None | |
|
| The IP Core is a fully configurable video timing generator with the ability to support any video resolution up to 216 x 216 pixels in size. The module is compatible with a wide range of video DACs, CODECs and transceivers and provides a flexible solution for displaying digital or analogue video on an external TV, monitor or flat panel display. The module is capable of clock speeds in excess of 400 MHz on some FPGA platforms, making it ideal for the latest generation HD and UHD video solutions. After resynchronizing the input pixels to the pixel-clock domain , the controller locks to the first frame (or field) of video. Once frame-lock is achieved, pixels are supplied on demand to the video timing control unit. This module generates the correct RGB video, sync and blanking information depending on the chosen timing parameters. Application Legacy (SD) and analogue video applications Digital TV and multimedia solutions HD, UHD and SUHD next generation digital video | Introduction | |||||
| μIP | Price | Logic Gate Count | Clock Rate | Technology | Ratings | |
|---|---|---|---|---|---|---|