Needhelp
?
| 14-Bit 3 MSPS ADC in GSMC110nm | 60000 Points | 32.000 K μm^2 | 3 MHz | 110 nm |  |
|
| UIP_ADC14_3M_245303 is compact and low power 14-bit analog-to-digital converter silicon IP. It has 20 single-end input channel selection multiplexer or 10 differential input channels selection. This ADC uses fully differential SAR architecture optimized for low power and small area. The ADC is designed for high dynamic performance for input frequencies up to Nyquist rate. This ADC consumes 150 uA at 3 MSPS operation and occupies silicon area of 0.32 mm2 . The ADC has high immunity to substrate noise and is ideal for SoC integration. APPLICATIONS General purpose data acquisition Battery monitory system Temperature monitory system | Introduction | |||||
| 14-Bit 3 MSPS ADC in GSMC110nm | By Quotes | 322.000 K μm^2 | 3 MHz | 110 nm | |
|
| MCR_GS110_ADC14 is compact and low power 14-bit analog-to-digital converter silicon IP. It has 20 single-end input channel selection multiplexer or 10 differential input channels selection. This ADC uses fully differential SAR architecture optimized for low The ADC is designed for high dynamic performance for input frequencies up to Nyquist rate. | Introduction | |||||
| 10-Bit 1MSPS Cyclic A/D Converter | By Quotes | 300.000 K μm^2 | 10.12 MHz | 250 nm | |
|
| This IP is a 1MSPS , single supply , 10-bit analog-to-digital converter (ADC) that combines a low cost, high speed CMOS process and a novel architecture. It is a complete ADC with an on chip, high performance sample-and-hold amplifier and voltage reference. An external reference can be chosen to suit the dc accuracy and temperature drift requirements of the application. The device uses a cyclic architecture with digital error correction logic to guarantee no missing code over the full operating range. The input of this ADC is highly flexible. A truly differential input structure allows for both single-ended and differential input interface of varying span. The sample-and-hold amplifier (SHA) is equally suited for multiplexed systems that switched full-scale voltage levels in successive channels as well as sampling single-channel inputs at frequencies up to and beyond the Nyquist rate of 500KHz. | Introduction | |||||
| USB 3.2 G EN 1 OTG T RANSCEIVER | By Quotes | None | 12 MHz | 28 nm | |
|
| MIP300HJ0C │ MIP300NSHJ0C_SB are USB transceivers that provide a complete range of the host and peripheral functions. They are fully compliant with the USB 3.1 Gen1 and USB 2.0 OTG specifications. In the SuperSpeed mode, this transceiver is capable of transmitting or receiving data at 5.0 Gbps. When operating in the High-Speed mode, this transceiver is capable of transmitting or receiving data at 480 Mbps. | Introduction | |||||
| PLL with Multiple Output Frequency | By Quotes | 40.000 K μm^2 | 12.156 MHz | 130 nm | |
|
| The PLL is a 0.13μm Phase-Locked Loop (PLL) cell that provides a clock multiplier that can generate a stable 48M/96M/120MHz/156MHz clock from a 12MHz clock source. This is a “generic” PLL which integrates the Voltage-Controlled Oscillator (VCO), Phase-Frequency Detector, Low Pass Filter, Loop Divider and Post Divider. This PLL provides an operating voltage range of 1.08V ~ 1.32V, and an operating junction temperature range of -40˚ ~ 125℃. | Introduction | |||||
| 8051 Core | By Quotes | None | 20 MHz | None | |
|
| The 8051 has gained great popularity since its introduction and is estimated it is used in a large percentage of all embedded system products. The basic form of 8051 core includes several on-chip peripherals, like timers and counters, additionally there are 128 bytes of on-chip data memory and up to 4K bytes of on-chip program memory. | Introduction | |||||
| Oscillator - RC22MHz | By Quotes | None | 22 MHz | 180 nm | |
|
| The RC_OSC22M is a low power consumption internal Resistor/Capacitor oscillator with trimming operating frequency. This OSC needs input Bandgap reference voltage to maintain stable operating frequency and decrease power supply effects. The RC-oscillator cell is useful for applications that require an oscillator that utilizes non-external components and has a relaxed frequency tolerance. An enable / disable mode is provided to disable the oscillator. When the oscillator is in the disable mode, the output (CLK22M) goes to a logic level low. It is processed using SMIC’s 0.35μm logic process with an operating supply voltage range of 2.0V ~ 5.5V and a junction temperature range of -40˚ ~ 125˚C. | Introduction | |||||
| 12-Bit 800KSPS Low Power SAR-ADC | By Quotes | None | 25 MHz | 180 nm | |
|
| The SAR-ADC is a low power ADC that is implemented in Successive Approximation architecture. It can provide 12-bit resolution capability with only 3V supply voltage. It accepts an analog input range from 0 to VCC and digitizes the input at a maximum sampling frequency rate of 800KHz at 5V supply voltage. This ADC also includes MUX design to select 0 of 7 analog inputs. The power dissipation is less than 5mW with 5V power supply. This SAR-ADC is implemented in SMIC 0.18μm generic CMOS technology. | Introduction | |||||
| Rapid IO PHY in 65nm | By Quotes | 2.295 μm^2 | 25 MHz | 65 nm | |
|
| The IP is designed for chips that perform high bandwidth data communication while operating at low power consumption. It can also be used in any serial interface where timing and electrical specification can be satisfied. This IP has four individual Transmitter (TX) and Receiver (RX) channels, and one common phase lock loop (PLL). | Introduction | |||||
| USB 3.0 PHY in 110nm | By Quotes | 1.000 M μm^2 | 25 MHz | 110 nm | |
|
| The IP is a high speed SERDES macro which complies with USB3.0 electrical interface specification. This macro can be easily fabricated to form multiple lanes and implemented in USB systems design, both Host and Device.The IP is supported USB3.0 Super Speed (5Gbps) protocol and data rate. | Introduction | |||||
| μIP | Price | Logic Gate Count | Clock Rate | Technology | Ratings | |
|---|---|---|---|---|---|---|