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| MIPI M-PHY Gear 4 IP in TSMC 12nm FFC | By Quotes | None | 11 GHz | 12 nm |  |
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| MIPI M-PHY Gear 4 IP is compliant with the latest MIPI. Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification. A serial interface technology with high bandwidth capabilities and supports HS Gear4 rates up to 11.6Gbps, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. The MIPI M-PHY Gear 4 IP compliant to the RMMI interface which allows UniPro controller and UFS Controller. | Introduction | |||||
| MIPI M-PHY Gear 4 IP in TSMC 28nm HPC+ | By Quotes | None | 11 GHz | 28 nm | |
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| MIPI M-PHY Gear 4 IP is compliant with the latest MIPI. Alliance M-PHY v4.1 Specification, UniPro v1.8 Specification, and Universal Flash Storage (UFS) v3.0 Specification. A serial interface technology with high bandwidth capabilities and supports HS Gear4 rates up to 11.6Gbps, which is particularly developed for mobile applications to obtain low pin count combined with very good power efficiency. The MIPI M-PHY Gear 4 IP compliant to the RMMI interface which allows UniPro controller and UFS Controller. | Introduction | |||||
| 8-Bit 7 GSPS SAR ADC | By Quotes | 300.000 K μm^2 | 7 GHz | 16 nm | |
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| This IP is compact and low power 8-bit Time interleaved SAR analog-to-digital converter silicon IP.This ADC uses fully differential SAR architecture optimized for low power and small silicon area. APPLICATIONS Serdes Receiver Coherent Transceivers Data acquisition | Introduction | |||||
| WiFi Frequency Synthesizer IP In 2.4GHz Band | 100000 Points | 200.000 K μm^2 | 3.2 GHz | 55 nm | |
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| The frequency synthesizer uses a single 1.25V power supply. Good noise immunity allows this IP to be integrated in a noisy SOC environment. The synthesizer operates at 1.5X WiFi 2.4GHz band for wireless application. | Introduction | |||||
| 2.4G PLL(UMC 28nm HPC) | By Quotes | 24.000 K μm^2 | 2.4 GHz | 28 nm | |
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| Clock output 2.4GHz Input clock 10 ~ 50MHz Current consumption: < 4mA Supply: 1.8V / 0.9V UMC 28nm HPC | Introduction | |||||
| HEART(High Efficient Accumulative Repairing Technical) | 50000 Points | 5.250 K Gates | 2.2 GHz | 40 nm | |
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| HEART can efficient repair faulty SRAM after using BRAINS. SoCs can mantain correctness of functions and avoid fatal error of system reault in SRAM's defect through SRAM's repairing technical. HEART is SRAM accumulative repairing technical, and it combines advantages of Soft-repair and Hard-repair. HEART supports internal registers of SoCs and external storages of SoCs to record SRAM's faulty information. Once SoCs have new SRAM's defect after using them for a long time, users can repeated repair SRAM's defect through HEART. In addtion, HEART also support "On-Demad" testing and repairing requirement. It means that users can enable system registers of SoCs or signal of HEART to test and repair SRAM at one when SoCs have fatal error situations. | Introduction | |||||
| NVM test and repair | 60000 Points | 5.250 K Gates | 2.2 GHz | 40 nm | |
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| HEART (High Efficient Accumulative Repairing Technical) is a built-in self-repair (BISR) mechanism which uses to recover errors detected after memory testing and to improve yield rate. This mechanism is implemented with spare memories and a built-in redundancy analyze (BIRA) logics which is designed to allocate the redundancy. It needs a storable device (eFuse, OTP or registers) to store testing results after analysis. We provides an efficient accumulative repairing solution to combine advantages of soft BISR mechanism and hard BISR mechanism for improving yield rate. | Introduction | |||||
| PLL 2000M UMC 28 nm logic and Mixed-Mode HPC process | By Quotes | 230.000 μm^2 | 2 GHz | 28 nm | |
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| A Phase-Locked Loop (PLL) circuit used to generate the high-speed clock with an operating frequency up to 2000 MHz. This PLL is designed by using the UMC 28 nm logic and Mixed-Mode HPC process. It can be integrated into a chip to generate an accurate clock. | Introduction | |||||
| PLL 1600M UMC 28 nm logic and Mixed-Mode HPC process | By Quotes | 270.000 μm^2 | 1.6 GHz | 28 nm | |
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| A Phase-Locked Loop (PLL) with an operating frequency ranging from 200 MHz to 1600 MHz. This PLL is designed with the UMC 28 nm logic and Mixed-Mode HPC process. It can be integrated into a chip to generate a high-speed clock. The embedded divide-by-4 loop divider allows users to boost the output frequency of up to 1600 MHz. | Introduction | |||||
| BRAINS | 50000 Points | 5.250 K Gates | 1.2 GHz | 40 nm | |
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| With improvement of technology node and IC design is geting more complex, the ratio of embedded memory in SoCs have been exceeding 50%. The fault types of memory are getting complex. The Memory BIST (Built-In Self-Test) is generated for efficient controlling IC cost. The traditional BIST method is inserted along with single memory. If there are many memories in SoCs, the area and testing time of SoCs are expanded a lot due to insertion of BIST. Therefore the SoCs' cost will increase rapidly because memory testing time is too long. We devoted in developing SRAM testing solutions for a long time. BRAINS is based on memory testing patents to reduce testing time and increase yield rate. In addition, BRAINS has many unique features to increase SoCs' reliability and stability. | Introduction | |||||
| μIP | Price | Logic Gate Count | Clock Rate | Technology | Ratings | |
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